- 制造厂商:TI
- 产品类别:逻辑和电压转换
- 技术类目:缓冲器、驱动器和收发器 - 反向缓冲器和驱动器
- 功能描述:具有三态输出的 8 通道、3V 至 5.5V 反相器
- 点击这里打开及下载74AC11240的技术文档资料
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This octal buffer/line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. This device provides inverting outputs and symmetrical active-low output-enable () inputs. This device features high fan-out and improved fan-in.
The 74AC11240 is organized as two 4-bit buffers/line drivers with separate inputs. When is low, the device passes inverted data from the A inputs to the Y outputs. When is high, the outputs are in the high-impedance state.
The 74AC11240 is characterized for operation from -40°C to 85°C.
- Flow-Through Architecture Optimizes PCB Layout
- Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
- EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
- 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (NT)
EPIC is a trademark of Texas Instruments Incorporated.
- Technology Family
- AC
- Supply voltage (Min) (V)
- 3
- Supply voltage (Max) (V)
- 5.5
- Number of channels (#)
- 8
- IOL (Max) (mA)
- 24
- IOH (Max) (mA)
- -24
- ICC (Max) (uA)
- 80
- Input type
- Standard CMOS
- Output type
- 3-State
- Features
- Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode
- Rating
- Catalog
74AC11240的完整型号有:74AC11240DBR、74AC11240DW、74AC11240PW,以下是这些产品的关键参数及官网采购报价:
74AC11240DBR,工作温度:-40 to 85,封装:SSOP (DB)-24,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网74AC11240DBR的批量USD价格:1.594(1000+)
74AC11240DW,工作温度:-40 to 85,封装:SOIC (DW)-24,包装数量MPQ:25个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网74AC11240DW的批量USD价格:1.594(1000+)
74AC11240PW,工作温度:-40 to 85,封装:TSSOP (PW)-24,包装数量MPQ:60个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网74AC11240PW的批量USD价格:1.594(1000+)
14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM
该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。