The 74ACT11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.

The control input is implemented specifically to accommodate cascading. When the is low, the parity tree is disabled and the PARITY ERROR output remains at a high logic level, regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.

The I/O control circuitry is designed so that the I/O port remains in the high-impedance state during power up or power down, to prevent bus glitches.

The 74ACT11286 is characterized for operation from -40°C to 85°C.

• Inputs Are TTL-Voltage Compatible
• Generates Either Odd or Even Parity for Nine Data Lines
• Cascadable for n-Bits Parity
• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
• EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N)

EPIC is a trademark of Texas Instruments Incorporated.

• Number of channels (#)
• 9
• Technology Family
• ACT
• Input type
• TTL-Compatible CMOS
• Output type
• Push-Pull
• Features
• Balanced outputs, Very high speed (tpd 5-10ns)

74ACT11286的完整型号有：74ACT11286D，以下是这些产品的关键参数及官网采购报价：

74ACT11286D，工作温度：-40 to 85，封装：SOIC (D)-14，包装数量MPQ：50个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网74ACT11286D的批量USD价格：1.631（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。