- 制造厂商:TI
- 产品类别:数据转换器
- 技术类目:模数转换器 (ADC) - 高速模数转换器 (>10MSPS)
- 功能描述:12 位、105MSPS 模数转换器 (ADC)
- 点击这里打开及下载ADS6124的技术文档资料
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ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies.
It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.
The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability.
The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so that the device comes up in the desired state after power-up.
ADS612X includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.
The devices are specified over the industrial temperature range (-40°C to 85°C).
- Maximum Sample Rate: 125 MSPS
- 12-Bit Resolution with No Missing Codes
- 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
- Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
- Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
- Clock Duty Cycle Stabilizer
- Internal Reference with Support for External Reference
- No External Decoupling Required for References
- Programmable Output Clock Position and Drive Strength to Ease Data Capture
- 3.3 V Analog and 1.8 V to 3.3 V Digital Supply
- 32-QFN Package (5 mm × 5 mm)
- Pin Compatible 12-Bit Family (ADS612X)
- APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems
- Sample rate (Max) (MSPS)
- 105
- Resolution (Bits)
- 12
- Number of input channels
- 1
- Interface type
- DDR LVDS, Parallel CMOS
- Analog input BW (MHz)
- 500
- Features
- Low Power
- Rating
- Catalog
- Input range (Vp-p)
- 2
- Power consumption (Typ) (mW)
- 374
- Architecture
- Pipeline
- SNR (dB)
- 71.5
- ENOB (Bits)
- 11.5
- SFDR (dB)
- 91
- Operating temperature range (C)
- -40 to 85
- Input buffer
- No
ADS6124的完整型号有:ADS6124IRHBR、ADS6124IRHBT,以下是这些产品的关键参数及官网采购报价:
ADS6124IRHBR,工作温度:-40 to 85,封装:VQFN (RHB)-32,包装数量MPQ:3000个,MSL 等级/回流焊峰值温度:Level-3-260C-168 HR,引脚镀层/焊球材料:NIPDAUAG,TI官网ADS6124IRHBR的批量USD价格:22.095(1000+)
ADS6124IRHBT,工作温度:-40 to 85,封装:VQFN (RHB)-32,包装数量MPQ:250个,MSL 等级/回流焊峰值温度:Level-3-260C-168 HR,引脚镀层/焊球材料:NIPDAUAG,TI官网ADS6124IRHBT的批量USD价格:24.095(1000+)
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如果给定 ADC 采样速率和有用信号的范围,该计算器可以确定第 2 至第 9 谐波是否会返送到有用信号的频带中。图表以图形方式显示了在出现奈奎斯特混叠后基本信号以及第 2 至第 9 谐波的位置。