The ADS6445/ADS6444 is a high performance 14 bit 125/105 MSPS quad channel A-D converter. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1 dB steps up to 6 dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.

An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14 bit data from each channel. In addition to the serial data streams, the frame and bit clocks also are transmitted as LVDS outputs.

The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye openings and improve signal integrity, easing capture by the receiver.

The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

The ADS644X has internal references, but also can support an external reference mode. The device is specified over –55°C to 125°C operating junction temperature range.

• Maximum Sample Rate: 125 MSPS
• 14-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5-dB Coarse Gain and up to 6-dB Programmable Fine Gain for SFDR/SNR Trade-Off
• Serialized LVDS Outputs with Programmable Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mVPP
• Internal Reference with External Reference Support
• No External Decoupling Required for References
• 3.3-V Analog and Digital Supply
• 64-pin QFN Package (9 mm × 9 mm)
• Feature Compatible Dual Channel Family

• Sample rate (Max) (MSPS)
• 105
• Resolution (Bits)
• 14
• Number of input channels
• 4
• Interface type
• Serial LVDS
• Analog input BW (MHz)
• 500
• Features
• High Performance
• Rating
• HiRel Enhanced Product
• Input range (Vp-p)
• 2
• Power consumption (Typ) (mW)
• 1350
• Architecture
• Pipeline
• SNR (dB)
• 73.8
• ENOB (Bits)
• 11.7
• SFDR (dB)
• 91
• Operating temperature range (C)
• -55 to 125
• Input buffer
• No

ADS6444-EP的完整型号有：ADS6444MRGCTEP、V62/08628-02XE，以下是这些产品的关键参数及官网采购报价：

ADS6444MRGCTEP，工作温度：-55 to 125，封装：VQFN (RGC)-64，包装数量MPQ：250个，MSL 等级/回流焊峰值温度：Level-3-260C-168 HR，引脚镀层/焊球材料：NIPDAU，TI官网ADS6444MRGCTEP的批量USD价格：150.292（1000+）

V62/08628-02XE，工作温度：-55 to 125，封装：VQFN (RGC)-64，包装数量MPQ：250个，MSL 等级/回流焊峰值温度：Level-3-260C-168 HR，引脚镀层/焊球材料：NIPDAU，TI官网V62/08628-02XE的批量USD价格：150.292（1000+）

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice

PSpice for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助?PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。

在?PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)