- 制造厂商：TI
- 产品类别：逻辑和电压转换
- 技术类目：触发器、锁存器和寄存器 - D 型锁存器
- 功能描述：CMOS 四路时钟控制“D”锁存器
- 点击这里打开及下载CD4042B的技术文档资料
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CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.
Information present at the data input is transferred to outputs Q and Q\ during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs.
The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
- Clock polarity control
- Q and Q\ outputs
- Common Clock
- Low power TTL compatible
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- 5-V, 10-V, and 15-V parametric ratings
- Noise margin (full package-temperature range) = 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Buffer storage
- Holding register
- General digital logic
Data sheet acquired from Harris Semiconductor
- Number of channels (#)
- 4
- Technology Family
- CD4000
- Supply voltage (Min) (V)
- 3
- Supply voltage (Max) (V)
- 18
- Input type
- Standard CMOS
- Output type
- CMOS
- Clock Frequency (Max) (MHz)
- 8
- IOL (Max) (mA)
- 2.4
- IOH (Max) (mA)
- -2.4
- ICC (Max) (uA)
- 600
- Features
- Standard speed (tpd > 50ns), High speed (tpd 10-50ns), Partial power down (Ioff)
CD4042B的完整型号有：CD4042BD、CD4042BDR、CD4042BDT、CD4042BDW、CD4042BE、CD4042BNSR、CD4042BPW，以下是这些产品的关键参数及官网采购报价：
CD4042BD，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4042BD的批量USD价格：.339（1000+）
CD4042BDR，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：2500个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4042BDR的批量USD价格：.139（1000+）
CD4042BDT，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：250个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4042BDT的批量USD价格：.339（1000+）
CD4042BDW，工作温度：-55 to 125，封装：SOIC (DW)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4042BDW的批量USD价格：.181（1000+）
CD4042BE，工作温度：-55 to 125，封装：PDIP (N)-16，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网CD4042BE的批量USD价格：.16（1000+）
CD4042BNSR，工作温度：-55 to 125，封装：SO (NS)-16，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4042BNSR的批量USD价格：.153（1000+）
CD4042BPW，工作温度：-55 to 125，封装：TSSOP (PW)-16，包装数量MPQ：90个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4042BPW的批量USD价格：.181（1000+）
14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM
该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
