CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.

The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

• 3-state outputs with common output ENABLE
• Separate SET and RESET inputs for each latch
• NOR and NAND configurations
• 5-V, 10-V, and 15-V parametric ratings
• Standardized symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
• Applications
  • Holding register in multi-register system
  • Four bits of independent storage with output ENABLE
  • Strobed register
  • General digital logic
  • CD4043B for positive logic systems
  • CD4044B for negative logic systems

Data sheet acquired from Harris Semiconductor

• Function
• RS latch
• Number of channels (#)
• 4
• Technology Family
• CD4000
• Supply voltage (Min) (V)
• 3
• Supply voltage (Max) (V)
• 18
• Input type
• Standard CMOS
• Output type
• 3-State
• Data rate (Max) (Mbps)
• 16
• IOL (Max) (mA)
• 2.4
• IOH (Max) (mA)
• -2.4
• Features
• Standard speed (tpd > 50ns), High speed (tpd 10-50ns), Partial power down (Ioff)

CD4044B的完整型号有：CD4044BD、CD4044BDR、CD4044BDT、CD4044BDW、CD4044BE、CD4044BNSR、CD4044BPWR，以下是这些产品的关键参数及官网采购报价：

CD4044BD，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4044BD的批量USD价格：.317（1000+）

CD4044BDR，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：2500个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4044BDR的批量USD价格：.106（1000+）

CD4044BDT，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：250个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4044BDT的批量USD价格：.317（1000+）

CD4044BDW，工作温度：-55 to 125，封装：SOIC (DW)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4044BDW的批量USD价格：.117（1000+）

CD4044BE，工作温度：-55 to 125，封装：PDIP (N)-16，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网CD4044BE的批量USD价格：.143（1000+）

CD4044BNSR，工作温度：-55 to 125，封装：SO (NS)-16，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4044BNSR的批量USD价格：.127（1000+）

CD4044BPWR，工作温度：-55 to 125，封装：TSSOP (PW)-16，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4044BPWR的批量USD价格：.106（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。