- 制造厂商:TI
- 产品类别:逻辑和电压转换
- 技术类目:逻辑门 - 组合门
- 功能描述:CMOS 双路 2 宽度 2 输入与或非门
- 点击这里打开及下载CD4085B的技术文档资料
- TI代理渠道,提供当日发货、严格的质量标准,满足您的目标价格
CD4085 contains a pair of AND-OR-INVERT gates, each consisting of two 2-input AND gates driving a 3-input NOR gate. Individual inhibit controls are provided for both A-O-I gates.
The CD4085B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
- Medium-speed operation - tPHL = 90 ns; tPLH = 125 ns (typ.) at 10 V
- Individual inhibit controls
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (over full package-temperature range):
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Technology Family
- CD4000
- Supply voltage (Min)
- 3
- Supply voltage (Max) (V)
- 18
- Number of channels (#)
- 2
- Inputs per channel
- 2
- IOL (Max) (mA)
- 6.8
- IOH (Max) (mA)
- -6.8
- Input type
- Standard CMOS
- Output type
- Push-Pull
- Features
- Standard speed (tpd > 50ns)
- Data rate (Max) (Mbps)
- 8
- Rating
- Catalog
- Operating temperature range (C)
- -55 to 125
CD4085B的完整型号有:CD4085BE、CD4085BM、CD4085BPWR,以下是这些产品的关键参数及官网采购报价:
CD4085BE,工作温度:-55 to 125,封装:PDIP (N)-14,包装数量MPQ:25个,MSL 等级/回流焊峰值温度:N/A for Pkg Type,引脚镀层/焊球材料:NIPDAU,TI官网CD4085BE的批量USD价格:.163(1000+)
CD4085BM,工作温度:-55 to 125,封装:SOIC (D)-14,包装数量MPQ:50个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD4085BM的批量USD价格:.143(1000+)
CD4085BPWR,工作温度:-55 to 125,封装:TSSOP (PW)-14,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD4085BPWR的批量USD价格:.143(1000+)
14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM
该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。