CD4508B dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE control. With the STROBE line in the high state, the data on the "D" inputs appear at the corresponding "Q" outputs provided the DISABLE line is in the low state. Changing the STROBE line to the low state locks the data into the latch. A high on the reset line forces the outputs to a low level regardless of the state of the STROBE input. The outputs are forced to the high-impedance state for bus line applications by a high level on the DISABLE input.

The CD4508B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (PW and PWR suffixes).

The CD4508B is similar to industry type MC14508.

• Two independent 4-bit latches
• Individual master reset for each 4-bit latch
• 3-state outputs with high-impedance state for bus line applications
• Medium-speed operation: tPHL = tPLH = 70 ns (typ.) at VDD = 10 V and CL = 50 pF
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Standardized, symmetrical output characteristics
• Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range) = 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
• Applications:
  • Buffer storage
  • Holding registers
  • Data storage and multiplexing

• Number of channels (#)
• 8
• Technology Family
• CD4000
• Supply voltage (Min) (V)
• 3
• Supply voltage (Max) (V)
• 18
• Input type
• Standard CMOS
• Output type
• 3-State
• Clock Frequency (Max) (MHz)
• 8
• IOL (Max) (mA)
• 2.4
• IOH (Max) (mA)
• -2.4
• ICC (Max) (uA)
• 3000
• Features
• Standard speed (tpd > 50ns), High speed (tpd 10-50ns), Partial power down (Ioff)

CD4508B的完整型号有：CD4508BM、CD4508BM96、CD4508BNSR、CD4508BPW，以下是这些产品的关键参数及官网采购报价：

CD4508BM，工作温度：-55 to 125，封装：SOIC (DW)-24，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4508BM的批量USD价格：.528（1000+）

CD4508BM96，工作温度：-55 to 125，封装：SOIC (DW)-24，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4508BM96的批量USD价格：.447（1000+）

CD4508BNSR，工作温度：-55 to 125，封装：SO (NS)-24，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4508BNSR的批量USD价格：.487（1000+）

CD4508BPW，工作温度：-55 to 125，封装：TSSOP (PW)-24，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4508BPW的批量USD价格：.447（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。