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CD4536B的基本参数
  • 制造厂商:TI
  • 产品类别:逻辑和电压转换
  • 技术类目:专用逻辑 IC - 数字计时 IC
  • 功能描述:CMOS 可编程计时器
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CD4536B的产品详情:

CD4536B is a programmable timer consisting of 24 ripple-binary counter stages. The salient feature of this device is its flexibility. The device can count from 1 to 224 or the first 8 stages can be bypassed to allow an output, selectable by a 4-bit code, from any one of the remaining 16 stages. It can be driven by an external clock or an RC oscillator that can be constructed using on-chip components. Input IN1 serves as either the external clock input or the input to the on-chip RC oscillator. OUT1 and OUT2 are connection terminals for the external RC components. In addition, an on-chip monostable circuit is provided to allow a variable pulse width output. Various timing functions can be achieved using combinations of these capabilities.

A logic 1 on the 8-BYPASS input enables a bypass of the first 8 stages and makes stage 9 the first counter stage of the last 16 stages. Selection of 1 of 16 outputs is accomplished by the decoder and the BCD inputs A, B, C and D. MONO IN is the timing input for the on-chip monostable oscillator. Grounding of the MONO IN terminal through a resistor of 10K ohms or higher, disables the one-shot circuit and connects the decoder directly to the DECODE OUT terminal. A resistor to VDD and a capacitor to ground from the MONO IN terminal enables the one-shot circuit and control its pulse width.

A fast test mode is enabled by a logic 1 on 8-BYPASS, SET, and RESET. This mode divides the 24-stage counter into three 8-stage sections to facilitate a fast test sequence.

The CD4536B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (DW, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4536B的优势和特性:
  • 24 flip-flop stages - - counts from 20 to 224
  • Last 16 stages selectable by BCD select code
  • Bypass input allows bypassing first 8 stages
  • On-chip RC oscillator provision
  • Clock inhibit input
  • Schmitt-trigger in clock line permits operation with very long rise and fall times
  • On-chip monostable output provision
  • Typical fCL = 3 MHz at VDD = 10 V
  • Test mode allows fast test sequence
  • Set and reset inputs
  • Capable of driving two low power TTL loads, one lower-power Schottky load, or two HTL loads over the rated temperature range
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
CD4536B的参数(英文):
  • Technology Family
  • CD4000
  • Bits (#)
  • 4
  • Supply voltage (Min) (V)
  • 3
  • Supply voltage (Max) (V)
  • 18
  • Input type
  • Standard CMOS
  • Output type
  • Push-Pull
  • ICC (Max) (uA)
  • 100
  • IOL (Max) (mA)
  • 4
  • IOH (Max) (mA)
  • -4
CD4536B具体的完整产品型号参数及价格(美元):

CD4536B的完整型号有:CD4536BDW、CD4536BDWR、CD4536BE、CD4536BNSR、CD4536BPW、CD4536BPWR,以下是这些产品的关键参数及官网采购报价:

CD4536BDW,工作温度:-55 to 125,封装:SOIC (DW)-16,包装数量MPQ:40个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD4536BDW的批量USD价格:0.47(1000+)

CD4536BDWR,工作温度:-55 to 125,封装:SOIC (DW)-16,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD4536BDWR的批量USD价格:0.27(1000+)

CD4536BE,工作温度:-55 to 125,封装:PDIP (N)-16,包装数量MPQ:25个,MSL 等级/回流焊峰值温度:N/A for Pkg Type,引脚镀层/焊球材料:NIPDAU,TI官网CD4536BE的批量USD价格:0.243(1000+)

CD4536BNSR,工作温度:-55 to 125,封装:SO (NS)-16,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD4536BNSR的批量USD价格:0.216(1000+)

CD4536BPW,工作温度:-55 to 125,封装:TSSOP (PW)-16,包装数量MPQ:90个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD4536BPW的批量USD价格:0.398(1000+)

CD4536BPWR,工作温度:-55 to 125,封装:TSSOP (PW)-16,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD4536BPWR的批量USD价格:0.198(1000+)

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CD4536B的评估套件:

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

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