- 制造厂商：TI
- 产品类别：逻辑和电压转换
- 技术类目：触发器、锁存器和寄存器 - 计数器
- 功能描述：高速 CMOS 逻辑 8 级同步减计数器
- 点击这里打开及下载CD54HC40103的技术文档资料
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The ’HC40103 and CD74HCT40103 are manufactured with high speed silicon gate technology and consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The 40103 contains a single 8-bit binary counter. Each has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the TC\ output are active-low logic.
In normal operation, the counter is decremented by one count on each positive transition of the CLOCK (CP). Counting is inhibited when the TE\ input is high. The TC\ output goes low when the count reaches zero if the TE\ input is low, and remains low for one full clock period.
When the PE\ input is low, data at the P0-P7 inputs are clocked into the counter on the next positive clock transition regardless of the state of the TE\ input. When the PL\ input is low, data at the P0-P7 inputs are asynchronously forced into the counter regardless of the state of the PE\, TE\, or CLOCK inputs. Input P0-P7 represent a single 8-bit binary word for the 40103. When the MR input is low, the counter is asynchronously cleared to its maximum count of 25510, regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table.
If all control inputs except TE\ are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 10016 or 25610 clock pulses long.
The 40103 may be cascaded using the TE\ input and the TC\ output, in either a synchronous or ripple mode. These circuits possess the low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits and can drive up to 10 LSTTL loads.
- Synchronous or Asynchronous Preset
- Cascadable in Synchronous or Ripple Mode
- Fanout (Over Temperature Range)
- Standard Outputs . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . –55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1μA at VOL, VOH
Data sheet acquired from Harris Semiconductor
- Function
- Counter
- Bits (#)
- 8
- Technology Family
- HC
- Supply voltage (Min) (V)
- 2
- Supply voltage (Max) (V)
- 6
- Input type
- Standard CMOS
- Output type
- Push-Pull
- Features
- Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode
CD54HC40103的完整型号有：5962-9055301EA、CD54HC40103F、CD54HC40103F3A，以下是这些产品的关键参数及官网采购报价：
5962-9055301EA，工作温度：-55 to 125，封装：CDIP (J)-16，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网5962-9055301EA的批量USD价格：16.17（1000+）
CD54HC40103F，工作温度：-55 to 125，封装：CDIP (J)-16，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网CD54HC40103F的批量USD价格：10.106（1000+）
CD54HC40103F3A，工作温度：-55 to 125，封装：CDIP (J)-16，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网CD54HC40103F3A的批量USD价格：16.17（1000+）
5962-9055301EA，工作温度：-55 to 125，封装：CDIP (J)-16，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网5962-9055301EA的批量USD价格：16.17（1000+）
CD54HC40103F，工作温度：-55 to 125，封装：CDIP (J)-16，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网CD54HC40103F的批量USD价格：10.106（1000+）
CD54HC40103F3A，工作温度：-55 to 125，封装：CDIP (J)-16，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网CD54HC40103F3A的批量USD价格：16.17（1000+）
