- 制造厂商:TI
- 产品类别:逻辑和电压转换
- 技术类目:触发器、锁存器和寄存器 - 移位寄存器
- 功能描述:8 位串行输入/并行输出移位寄存器
- 点击这里打开及下载CD74AC164的技术文档资料
- TI代理渠道,提供当日发货、严格的质量标准,满足您的目标价格
The AC164 and ACT164 are 8-bit serial-in/parallel-out shift registers with asynchronous reset that utilize Advanced CMOS Logic technology. Data is shifted on the positive edge of the clock (CP). A LOW on the Master Reset (MR\) pin resets the shift register and all outputs go to the LOW state regardless of the input conditions. Two Serial Data inputs (DS1 and DS2) are provided; either one can be used as a Data Enable control.
- Buffered Inputs
- Typical Propagation Delay
- 6ns at VCC = 5V, TA = 25°C, CL = 50pF
- Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
- SCR-Latchup-Resistant CMOS Process and Circuit Design
- Speed of Bipolar FAST?/AS/S with Significantly Reduced Power Consumption
- Balanced Propagation Delays
- AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
- ±24mA Output Drive Current
- Fanout to 15 FAST? ICs
- Drives 50 Transmission Lines
FAST? is a Trademark of Fairchild Semiconductor.
- Configuration
- Serial-in, Parallel-out
- Bits (#)
- 8
- Technology Family
- AC
- Supply voltage (Min) (V)
- 1.5
- Supply voltage (Max) (V)
- 5.5
- Input type
- Standard CMOS
- Output type
- Push-Pull
- Clock Frequency (MHz)
- 75
- IOL (Max) (mA)
- 24
- IOH (Max) (mA)
- -24
- ICC (Max) (uA)
- 160
- Features
- Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode
CD74AC164的完整型号有:CD74AC164E、CD74AC164M、CD74AC164M96,以下是这些产品的关键参数及官网采购报价:
CD74AC164E,工作温度:-55 to 125,封装:PDIP (N)-14,包装数量MPQ:25个,MSL 等级/回流焊峰值温度:N/A for Pkg Type,引脚镀层/焊球材料:NIPDAU,TI官网CD74AC164E的批量USD价格:0.215(1000+)
CD74AC164M,工作温度:-55 to 125,封装:SOIC (D)-14,包装数量MPQ:50个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74AC164M的批量USD价格:0.391(1000+)
CD74AC164M96,工作温度:-55 to 125,封装:SOIC (D)-14,包装数量MPQ:2500个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74AC164M96的批量USD价格:0.191(1000+)
14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM
该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。