The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

• Inputs Are TTL-Voltage Compatible
• Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
• Balanced Propagation Delays
• ±24-mA Output Drive Current
  • Fanout to 15 F Devices
• SCR-Latchup-Resistant CMOS Process and Circuit Design
• Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

• Number of channels (#)
• 2
• Technology Family
• ACT
• Supply voltage (Min) (V)
• 4.5
• Supply voltage (Max) (V)
• 5.5
• Input type
• TTL
• Output type
• Push-Pull
• Clock Frequency (MHz)
• 100
• ICC (Max) (uA)
• 80
• IOL (Max) (mA)
• 24
• IOH (Max) (mA)
• -24
• Features
• Balanced outputs, Negative edge triggered, High speed (tpd 10-50ns), Positive input clamp diode, Preset, Clear

CD74ACT112的完整型号有：CD74ACT112M、CD74ACT112M96，以下是这些产品的关键参数及官网采购报价：

CD74ACT112M，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74ACT112M的批量USD价格：.328（1000+）

CD74ACT112M96，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：2500个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74ACT112M96的批量USD价格：.281（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。