The CD74ACT74 dual positive-edge-triggered device is a D-type flip-flop.

A low level at the preset (PRE) or (CLR) clear inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

• Qualified for Automotive Applications
• Inputs Are TTL-Voltage Compatible
• Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
• Balanced Propagation Delays
• ±24-mA Output Drive Current
  • Fanout to 15 F Devices
• SCR-Latchup-Resistant CMOS Process and Circuit Design

• Number of channels (#)
• 2
• Technology Family
• ACT
• Supply voltage (Min) (V)
• 4.5
• Supply voltage (Max) (V)
• 5.5
• Input type
• TTL-Compatible CMOS
• Output type
• Push-Pull
• Clock Frequency (Max) (MHz)
• 85
• IOL (Max) (mA)
• 24
• IOH (Max) (mA)
• -24
• ICC (Max) (uA)
• 80
• Features
• Balanced outputs, Very high speed (tpd 5-10ns), Positive input clamp diode

CD74ACT74-Q1的完整型号有：CD74ACT74QM96G4Q1，以下是这些产品的关键参数及官网采购报价：

CD74ACT74QM96G4Q1，工作温度：-40 to 125，封装：SOIC (D)-14，包装数量MPQ：2500个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74ACT74QM96G4Q1的批量USD价格：.269（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。