- 制造厂商:TI
- 产品类别:逻辑和电压转换
- 技术类目:专用逻辑 IC - 单稳多谐振荡器(单稳态)
- 功能描述:具有复位功能的高速 CMOS 逻辑双路可重触发单稳态多谐振荡器
- 点击这里打开及下载CD74HC123的技术文档资料
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The HC123, HCT123, CD74HC423 and CD74HCT423 are dual monostable multivibrators with resets. They are all retriggerable and differ only in that the 123 types can be triggered by a negative to positive reset pulse; whereas the 423 types do not have this feature. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of Rx and CX provides a wide range of output pulse widths from the Q and Q\ terminals. Pulse triggering on the A\ and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses.
Once triggered, the output pulse width may be extended by retriggering inputs A\ and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing edge triggering (A)\ and leading edge triggering (B) inputs are provided for triggering from either edge of the input pulse. If either Mono is not used each input on the unused device (A\, B, and R\) must be terminated high or low.
The minimum value of external resistance, Rx is typically 5k. The minimum value external capacitance, CX, is 0pF. The calculation for the pulse width is tW = 0.45 RXCX at VCC = 5V.
- Overriding Reset Terminates Output Pulse
- Triggering From the Leading or Trailing Edge
- Q and Q\ Buffered Outputs
- Separate Resets
- Wide Range of Output-Pulse Widths
- Schmitt Trigger on Both A\ and B Inputs
- Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . –55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1μA at VOL, VOH
- Number of channels (#)
- 2
- Supply voltage (Min) (V)
- 2
- Supply voltage (Max) (V)
- 6
- Technology Family
- HC
- Input type
- Standard CMOS
- Output type
- Push-Pull
- ICC (uA)
- 80
- IOL (Max) (mA)
- 5.2
- IOH (Max) (mA)
- -5.2
- Features
- Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode, Retriggerable
CD74HC123的完整型号有:CD74HC123E、CD74HC123M、CD74HC123M96、CD74HC123M96G4、CD74HC123MT、CD74HC123NSR、CD74HC123PW、CD74HC123PWR、CD74HC123PWRG4、CD74HC123PWT,以下是这些产品的关键参数及官网采购报价:
CD74HC123E,工作温度:-55 to 125,封装:PDIP (N)-16,包装数量MPQ:25个,MSL 等级/回流焊峰值温度:N/A for Pkg Type,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC123E的批量USD价格:.145(1000+)
CD74HC123M,工作温度:-55 to 125,封装:SOIC (D)-16,包装数量MPQ:40个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC123M的批量USD价格:.326(1000+)
CD74HC123M96,工作温度:-55 to 125,封装:SOIC (D)-16,包装数量MPQ:2500个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC123M96的批量USD价格:.126(1000+)
CD74HC123M96G4,工作温度:-55 to 125,封装:SOIC (D)-16,包装数量MPQ:2500个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC123M96G4的批量USD价格:.145(1000+)
CD74HC123MT,工作温度:-55 to 125,封装:SOIC (D)-16,包装数量MPQ:250个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC123MT的批量USD价格:.326(1000+)
CD74HC123NSR,工作温度:-55 to 125,封装:SO (NS)-16,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC123NSR的批量USD价格:.151(1000+)
CD74HC123PW,工作温度:-55 to 125,封装:TSSOP (PW)-16,包装数量MPQ:90个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC123PW的批量USD价格:.326(1000+)
CD74HC123PWR,工作温度:-55 to 125,封装:TSSOP (PW)-16,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC123PWR的批量USD价格:.126(1000+)
CD74HC123PWRG4,工作温度:-55 to 125,封装:TSSOP (PW)-16,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC123PWRG4的批量USD价格:.145(1000+)
CD74HC123PWT,工作温度:-55 to 125,封装:TSSOP (PW)-16,包装数量MPQ:250个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC123PWT的批量USD价格:.326(1000+)
14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM
该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。