The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds.

The two modes of operation, shift right (Q₀-Q₁) and parallel load, are controlled by the state of the Parallel Enable (PE)\ input. Serial data enters the first flip-flop (Q₀) via the J and K\ inputs when the PE\ input is high, and is shifted one bit in the direction Q₀-Q₁-Q₂-Q₃ following each Low to High clock transition. The J and K\ inputs provide the flexibility of the JK-type input for special applications and by tying the two pins together, the simple D-type input for general applications. The device appears as four common-clocked D flip-flops when the PE\ input is Low. After the Low to High clock transition, data on the parallel inputs (D0-D3) is transferred to the respective Q₀-Q₃ outputs. Shift left operation (Q₃-Q₂) can be achieved by tying the Q_n outputs to the Dn-1 inputs and holding the PE\ input low.

All parallel and serial data transfers are synchronous, occurring after each Low to High clock transition. The ’HC195 series utilizes edge triggering; therefore, there is no restriction on the activity of the J, K\, Pn and PE\ inputs for logic operations, other than set-up and hold time requirements. A Low on the asynchronous Master Reset (MR)\ input sets all Q outputs Low, independent of any other input condition.

• Asynchronous Master Reset
• J, K\,(D) Inputs to First Stage
• Fully Synchronous Serial or Parallel Data Transfer
• Shift Right and Parallel Load Capability
• Complementary Output From Last Stage
• Buffered Inputs
• Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25°C
• Fanout (Over Temperature Range)
  • Standard Outputs . . . . 10 LSTTL Loads
  • Bus Driver Outputs . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . –55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
  • 2V to 6V Operation
  • High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V

Data sheet acquired from Harris Semiconductor

• Configuration
• Universal
• Bits (#)
• 4
• Technology Family
• HC
• Supply voltage (Min) (V)
• 2
• Supply voltage (Max) (V)
• 6
• Input type
• Standard CMOS
• Output type
• Push-Pull
• Clock Frequency (MHz)
• 60
• IOL (Max) (mA)
• 5.2
• IOH (Max) (mA)
• -5.2
• ICC (Max) (uA)
• 160
• Features
• Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

CD74HC195的完整型号有：CD74HC195E、CD74HC195M、CD74HC195M96、CD74HC195NSR、CD74HC195PW、CD74HC195PWR，以下是这些产品的关键参数及官网采购报价：

CD74HC195E，工作温度：-55 to 125，封装：PDIP (N)-16，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网CD74HC195E的批量USD价格：.284（1000+）

CD74HC195M，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74HC195M的批量USD价格：.295（1000+）

CD74HC195M96，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：2500个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74HC195M96的批量USD价格：.25（1000+）

CD74HC195NSR，工作温度：-55 to 125，封装：SO (NS)-16，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74HC195NSR的批量USD价格：.272（1000+）

CD74HC195PW，工作温度：-55 to 125，封装：TSSOP (PW)-16，包装数量MPQ：90个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74HC195PW的批量USD价格：.295（1000+）

CD74HC195PWR，工作温度：-55 to 125，封装：TSSOP (PW)-16，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74HC195PWR的批量USD价格：.254（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。