- 制造厂商:TI
- 产品类别:逻辑和电压转换
- 技术类目:逻辑门 - 与非门
- 功能描述:单路 8 输入、2V 至 6V 与非门
- 点击这里打开及下载CD74HC30的技术文档资料
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This device contains one independent 8-input NAND gate. Each gate performs the Boolean function Y = A ● B ● C ● D ● E ● F ● G ● H in positive logic.
- Buffered inputs
- Wide operating voltage range: 2Vto6V
- Wide operating temperature range: –55°Cto+125°C
- Supports fanout up to 10 LSTTL loads
- Significant power reduction compared to LSTTL logic ICs
- Technology Family
- HC
- Supply voltage (Min) (V)
- 2
- Supply voltage (Max) (V)
- 6
- Number of channels (#)
- 1
- Inputs per channel
- 8
- IOL (Max) (mA)
- 5.2
- IOH (Max) (mA)
- -5.2
- Input type
- Standard CMOS
- Output type
- Push-Pull
- Features
- High speed (tpd 10- 50ns)
- Data rate (Max) (Mbps)
- 28
- Rating
- Catalog
CD74HC30的完整型号有:CD74HC30E、CD74HC30M、CD74HC30M96、CD74HC30MT、CD74HC30NSR、CD74HC30PW、CD74HC30PWR、CD74HC30PWT,以下是这些产品的关键参数及官网采购报价:
CD74HC30E,工作温度:-55 to 125,封装:PDIP (N)-14,包装数量MPQ:25个,MSL 等级/回流焊峰值温度:N/A for Pkg Type,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC30E的批量USD价格:.115(1000+)
CD74HC30M,工作温度:-55 to 125,封装:SOIC (D)-14,包装数量MPQ:50个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC30M的批量USD价格:.3(1000+)
CD74HC30M96,工作温度:-55 to 125,封装:SOIC (D)-14,包装数量MPQ:2500个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:SN,TI官网CD74HC30M96的批量USD价格:.1(1000+)
CD74HC30MT,工作温度:-55 to 125,封装:SOIC (D)-14,包装数量MPQ:250个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC30MT的批量USD价格:.3(1000+)
CD74HC30NSR,工作温度:-55 to 125,封装:SO (NS)-14,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC30NSR的批量USD价格:.11(1000+)
CD74HC30PW,工作温度:-55 to 125,封装:TSSOP (PW)-14,包装数量MPQ:90个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC30PW的批量USD价格:.3(1000+)
CD74HC30PWR,工作温度:-55 to 125,封装:TSSOP (PW)-14,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:SN,TI官网CD74HC30PWR的批量USD价格:.1(1000+)
CD74HC30PWT,工作温度:-55 to 125,封装:TSSOP (PW)-14,包装数量MPQ:250个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网CD74HC30PWT的批量USD价格:.3(1000+)
14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM
该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。