The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2), and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (C_LD) and pin 8 (Gnd). For a frequency range of 100kHz to 10MHz, the lock detector capacitor should be 1000pF to 10pF, respectively.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 7046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.

• Center Frequency of 18MHz (Typ) at VCC = 5V, Minimum Center Frequency of 12MHz at VCC = 4.5V
• Choice of Two Phase Comparators
  • Exclusive-OR
  • Edge-Triggered JK Flip-Flop
• Excellent VCO Frequency Linearity
• VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
• Minimal Frequency Drift
• Zero Voltage Offset Due to Op-Amp Buffer
• Operating Power-Supply Voltage Range
  • VCO Section...3V to 6V
  • Digital Section...2V to 6V
• Fanout (Over Temperature Range)
  • Standard Outputs...10 LSTTL Loads
  • Bus Driver Outputs...15 LSTTL Loads
• Wide Operating Temperature Range... –55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
  • 2V to 6V Operation
  • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
  • CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH
• Applications
  • FM Modulation and Demodulation
  • Frequency Synthesis and Multiplication
  • Frequency Discrimination
  • Tone Decoding
  • Data Synchronization and Conditioning
  • Voltage-to-Frequency Conversion
  • Motor-Speed Control
  • Related Literature
    • AN8823, CMOS Phase-Locked-Loop Application Using the CD74HC/HCT7046A and CD74HC/HCT7046A

• Technology Family
• HC
• Bits (#)
• 1
• Supply voltage (Min) (V)
• 2
• Supply voltage (Max) (V)
• 6
• Input type
• Standard CMOS
• Output type
• Push-Pull
• ICC (Max) (uA)
• 160
• IOL (Max) (mA)
• 5.2
• IOH (Max) (mA)
• -5.2

CD74HC7046A的完整型号有：CD74HC7046AE、CD74HC7046AM、CD74HC7046AM96、CD74HC7046AMT，以下是这些产品的关键参数及官网采购报价：

CD74HC7046AE，工作温度：-55 to 125，封装：PDIP (N)-16，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网CD74HC7046AE的批量USD价格：1.035（1000+）

CD74HC7046AM，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74HC7046AM的批量USD价格：1.076（1000+）

CD74HC7046AM96，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：2500个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74HC7046AM96的批量USD价格：.911（1000+）

CD74HC7046AMT，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：250个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74HC7046AMT的批量USD价格：1.076（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。