- 制造厂商：TI
- 产品类别：逻辑和电压转换
- 技术类目：专用逻辑 IC - 数字多路复用器和编码器
- 功能描述：具有同向三态输出的高速 CMOS 逻辑四路 2 输入多路复用器
- 点击这里打开及下载CD74HCT257的技术文档资料
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The ’HC257 and ’HCT257 are quad 2-input multiplexers which select four bits of data from two sources under the control of a common Select Input (S). The Output Enable input (OE\) is active LOW. When OE\ is HIGH, all of the outputs (1Y-4Y) are in the high impedance state regardless of all other input conditions.
Moving data from two groups of registers to four common output buses is a common use of the 257. The state of the Select input determines the particular register from which the data comes. It can also be used as a function generator.
- Buffered Inputs
- Typical Propagation Delay (In to Output) = 12ns at VCC = 5V, CL = 15pF, TA = 25°C
- Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
- Wide Operating Temperature Range...–55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1μA at VOL, VOH
Data sheet acquired from Harris Semiconductor
- Technology Family
- HCT
- Function
- Digital Multiplexer
- Configuration
- 2:1
- Number of channels (#)
- 4
- Operating temperature range (C)
- -55 to 125
- Rating
- Catalog
CD74HCT257的完整型号有：CD74HCT257E、CD74HCT257M、CD74HCT257M96，以下是这些产品的关键参数及官网采购报价：
CD74HCT257E，工作温度：-55 to 125，封装：PDIP (N)-16，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网CD74HCT257E的批量USD价格：.246（1000+）
CD74HCT257M，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74HCT257M的批量USD价格：.417（1000+）
CD74HCT257M96，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：2500个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74HCT257M96的批量USD价格：.217（1000+）
14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM
该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
