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CD74HCT354的基本参数
  • 制造厂商:TI
  • 产品类别:逻辑和电压转换
  • 技术类目:专用逻辑 IC - 数字多路复用器和编码器
  • 功能描述:具有三态输出的高速 CMOS 逻辑 8 输入多路复用器/寄存器
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CD74HCT354的产品详情:

The CD54HC354, CD74HC354, and CD74HCT354 are data selectors/multiplexers that select one of eight sources. In both types, the data select bits S0, S1 and S2 are stored in transparent latches that are enabled by a low latch enable input, LE\.

In the HC/HCT354 the data enable input, E\, controls transparent latches that pass data to the outputs when E\ is high and latches in new data when E\ is low.

In both types the three-state outputs are controlled by three output-enable inputs OE1\, OE2\, and OE3.

CD74HCT354的优势和特性:
  • HC/HCT354
    • Transparent Data and Select Latches
  • Buffered Inputs
  • Three-State Complementary Outputs
  • Bus Line Driving Capability
  • Typical Propagation Delay: VCC = 5V, CL = 15pF, TA = 25°C
    • Data to Output = 18ns
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1μA at VOL, VOH

CD74HCT354的参数(英文):
  • Technology Family
  • HCT
  • Function
  • Digital Multiplexer
  • Configuration
  • 8:1
  • Number of channels (#)
  • 1
  • Operating temperature range (C)
  • -55 to 125
  • Rating
  • Catalog
CD74HCT354具体的完整产品型号参数及价格(美元):

CD74HCT354的完整型号有:CD74HCT354E,以下是这些产品的关键参数及官网采购报价:

CD74HCT354E,工作温度:-55 to 125,封装:PDIP (N)-20,包装数量MPQ:20个,MSL 等级/回流焊峰值温度:N/A for Pkg Type,引脚镀层/焊球材料:NIPDAU,TI官网CD74HCT354E的批量USD价格:.604(1000+)

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CD74HCT354的评估套件:

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

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