The CDCLVD2104 clock buffer distributes two clock inputs (IN0, IN1) to a total of 8 pairs of differential LVDS clock outputs (OUT0, OUT7). Each buffer block consists of one input and 4 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2104 is specifically designed for driving 50- transmission lines. If the input is in single ended mode, the appropriate bias voltage (V_{AC_REF}) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical “0”), if switched to a logical "1", one buffer with four outputs is disabled and another buffer with four outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2104 is packaged in small 28-pin, 5-mm × 5-mm QFN package.

• Dual 1:4 Differential Buffer
• Low Additive Jitter <300 fs, RMS in 10 kHz to 20 MHz
• Low Within Bank Output Skew of 35ps (Max)
• Universal Inputs Accept LVDS, LVPECL, LVCMOS
• One Input Dedicated for Four Output Buffers
• 8 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
• Clock Frequency up to 800 MHz
• 2.375–2.625V Device Power Supply
• LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
• Industrial Temperature Range –40°C to 85°C
• Packaged in 5mm × 5mm 28-Pin QFN (RHD)
• ESD Protection Exceeds 3 kV HBM, 1 kV CDM
• APPLICATIONS
  • Telecommunications/Networking
  • Medical Imaging
  • Test and Measurement Equipment
  • Wireless Communications
  • General Purpose Clocking

• Function
• Differential
• Additive RMS jitter (Typ) (fs)
• 171
• Output frequency (Max) (MHz)
• 800
• Number of outputs
• 8
• Output supply voltage (V)
• 2.5
• Core supply voltage (V)
• 2.5
• Output skew (ps)
• 35
• Features
• Dual 1:4 fanout, Universal inputs, Output enable control
• Operating temperature range (C)
• -40 to 85
• Rating
• Catalog
• Output type
• LVDS
• Input type
• LVCMOS, LVDS, LVPECL

CDCLVD2104的完整型号有：CDCLVD2104RHDR、CDCLVD2104RHDT，以下是这些产品的关键参数及官网采购报价：

CDCLVD2104RHDR，工作温度：-40 to 85，封装：VQFN (RHD)-28，包装数量MPQ：3000个，MSL 等级/回流焊峰值温度：Level-2-260C-1 YEAR，引脚镀层/焊球材料：NIPDAU，TI官网CDCLVD2104RHDR的批量USD价格：3.696（1000+）

CDCLVD2104RHDT，工作温度：-40 to 85，封装：VQFN (RHD)-28，包装数量MPQ：250个，MSL 等级/回流焊峰值温度：Level-2-260C-1 YEAR，引脚镀层/焊球材料：NIPDAU，TI官网CDCLVD2104RHDT的批量USD价格：4.435（1000+）

CDCLVD2102EVM — CDCLVD2102 评估模块

CDCLVD1204/CDCLVD2102 是高性能、低附加抖动时钟缓冲器。它们具有两个通用输入缓冲器，支持单端或差动时钟输入，可通过控制引脚（仅限 CDCLVD1204）进行选择。这两种器件还具有片上偏压发生器，该发生器可以为器件输入提供 LVDS 共模电压。评估模块 (EVM) 旨在演示 CDCLVD1204 或 CDCLVD2102 的电性能。不过，那些对 CDCLVD1208 或 CDCLVD2104 感兴趣的客户也可以使用此 EVM。这个完全组装且经过工厂测试的评估板允许对器件的所有功能进行全面验证。为达到最佳性能，该评估板配备有 SMA 连接器和受控良好的 50Ω 阻抗微带传输线。

CDCLVD2104 IBIS Model (Rev. B)

PSpice for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

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在?PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)

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