The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2106 clock buffer distributes two clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2106 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2106 is characterized for operation from –40°C to +85°C and is available in a 6-mm × 6-mm, VQFN-40 package.

• Dual 1:6 Differential Buffer
• Two Clock Inputs
• Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL
• 12 LVPECL Outputs
• Maximum Clock Frequency: 2 GHz
• Maximum Core Current Consumption: 92 mA
• Very Low Additive Jitter: <100 fs, RMS in 10-kHz to 20-MHz Offset Range
• 2.375-V to 3.6-V Device Power Supply
• Maximum Propagation Delay: 550 ps
• Maximum Within Bank Output Skew: 20 ps
• LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs
• Industrial Temperature Range: –40°C to +85°C
• Supports 105°C PCB Temperature (Measured with a Thermal Pad)
• Available in 6-mm × 6-mm, 40-Pin VQFN (RHA) Package
• ESD Protection Exceeds 2000 V (HBM)

• Function
• Differential
• Additive RMS jitter (Typ) (fs)
• 124
• Output frequency (Max) (MHz)
• 2000
• Number of outputs
• 12
• Output supply voltage (V)
• 2.5, 3.3
• Core supply voltage (V)
• 2.5, 3.3
• Output skew (ps)
• 20
• Features
• 2:12 fanout
• Operating temperature range (C)
• -40 to 85
• Rating
• Catalog
• Output type
• LVPECL
• Input type
• LVCMOS, LVDS, LVPECL

CDCLVP2106的完整型号有：CDCLVP2106RHAR、CDCLVP2106RHAT，以下是这些产品的关键参数及官网采购报价：

CDCLVP2106RHAR，工作温度：-40 to 85，封装：VQFN (RHA)-40，包装数量MPQ：2500个，MSL 等级/回流焊峰值温度：Level-3-260C-168 HR，引脚镀层/焊球材料：NIPDAU，TI官网CDCLVP2106RHAR的批量USD价格：6.006（1000+）

CDCLVP2106RHAT，工作温度：-40 to 85，封装：VQFN (RHA)-40，包装数量MPQ：250个，MSL 等级/回流焊峰值温度：Level-3-260C-168 HR，引脚镀层/焊球材料：NIPDAU，TI官网CDCLVP2106RHAT的批量USD价格：7.207（1000+）

CDCLVP2106EVM — CDCLVP2106 评估模块

CDCLVP2106 是一款高性能、低附加相位噪声时钟缓冲器。它具有两个通用输入缓冲器，支持单端或差动时钟输入。每个输入可馈给 6 个 LVPECL 输出。该器件还具有片上偏压发生器，它可以为器件输入提供 LVPECL 共模电压。此评估模块 (EVM) 旨在演示 CDCLVP2106 的电性能。这个完全组装且经过工厂测试的评估板允许对 CDCLVP2106 的所有功能进行全面验证。为达到最佳性能，该评估板配备有 50Ω SMA 连接器和受控良好的 50Ω 阻抗微带传输线。

CDCLVPxxxx IBIS Model (Rev. B)

PSpice for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助?PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。

在?PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)

CLOCK-TREE-ARCHITECT — 时钟树架构编程软件

时钟树架构是一款时钟树综合工具，可根据您的系统要求生成时钟树解决方案，从而帮助您简化设计流程。该工具从庞大的时钟产品数据库中提取数据，然后生成系统级多芯片时钟解决方案。