- 制造厂商：TI
- 产品类别：时钟和计时
- 技术类目：时钟缓冲器
- 功能描述：适用于 DRAM 应用且具有 10 个输出的 3.3V 锁相环路时钟驱动器
- 点击这里打开及下载CDCVF2510的技术文档资料
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The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCVF2510 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDCVF2510 is characterized for operation from 0°C to 85°C.
For application information see the application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL With Spread Spectrum Clocking (SSC) (SCAA039).
- Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
- Spread Spectrum Clock Compatible
- Operating Frequency 50 MHz to 175 MHz
- Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps
- Jitter (cyc - cyc) at 66 MHz to 166 MHz Is |70| ps
- Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices
- Available in Plastic 24-Pin TSSOP
- Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
- Distributes One Clock Input to One Bank of 10 Outputs
- External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
- 25- On-Chip Series Damping Resistors
- No External RC Network Required
- Operates at 3.3 V
NOT RECOMMENDED FOR NEW DESIGNS USE CDCVF2510A AS A REPLACEMENT
- Function
- Memory interface
- Additive RMS jitter (Typ) (fs)
- 70
- Output frequency (Max) (MHz)
- 175
- Number of outputs
- 10
- Output supply voltage (V)
- 3.3
- Core supply voltage (V)
- 3.3
- Output skew (ps)
- 100
- Features
- SDR
- Operating temperature range (C)
- 0 to 85
- Rating
- Catalog
- Output type
- LVTTL
- Input type
- LVTTL
CDCVF2510的完整型号有：CDCVF2510PW、CDCVF2510PWR、HPA00015PWR，以下是这些产品的关键参数及官网采购报价：
CDCVF2510PW，工作温度：0 to 85，封装：TSSOP (PW)-24，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CDCVF2510PW的批量USD价格：3.492（1000+）
CDCVF2510PWR，工作温度：0 to 85，封装：TSSOP (PW)-24，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CDCVF2510PWR的批量USD价格：2.975（1000+）
HPA00015PWR，工作温度：0 to 85，封装：TSSOP (PW)-24，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：-，引脚镀层/焊球材料：-，TI官网HPA00015PWR的批量USD价格：2.975（1000+）
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