- 制造厂商:TI
- 产品类别:接口
- 技术类目:高速串行器/解串器 - FPD-Link 串行器/解串器
- 功能描述:5MHz 至 35MHz 直流平衡 24 位汽车类 FPD-Link II 串行器
- 点击这里打开及下载DS90C241-Q1的技术文档资料
- TI代理渠道,提供当日发货、严格的质量标准,满足您的目标价格
The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths, which in turn reduces PCB layers, cable width, and connector size and pins.
The DS90C241 and DS90C124 incorporate LVDS signaling on the high-speed I/O. LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding and decoding supports AC-coupled interconnects.
- 5-MHz to 35-MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
- User Defined Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive Up to 10-Meter Shielded Twisted-Pair Cable
- User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
- Internal DC Balancing Encode and Decode (Supports AC-Coupling Interface With No External Coding Required)
- Individual Power-Down Controls for Both Transmitter and Receiver
- Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Required
- All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
- LOCK Output Flag to Ensure Data Integrity at Receiver Side
- Balanced TSETUP and THOLD Between RCLK and RDATA on Receiver Side
- PTO (Progressive Turnon) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
- All LVCMOS Inputs and Control Pins Have Internal Pulldown
- On-Chip Filters for PLLs on Transmitter and Receiver
- Temperature Range: –40°C to 105°C
- Greater Than 8-kV HBM ESD Tolerant
- Meets AEC-Q100 Compliance
- Power Supply Range: 3.3 V ± 10%
- 48-Pin TQFP Package
- Function
- Serializer
- Color depth (bpp)
- 18
- Input compatibility
- LVCMOS
- Pixel clock frequency (Max) (MHz)
- 35
- Output compatibility
- FPD-Link LVDS
- Features
- Low-EMI Point-to-Point Communication
- Operating temperature range (C)
- -40 to 105
DS90C241-Q1的完整型号有:DS90C241QVS/NOPB、DS90C241QVSX/NOPB,以下是这些产品的关键参数及官网采购报价:
DS90C241QVS/NOPB,工作温度:-40 to 105,封装:TQFP (PFB)-48,包装数量MPQ:250个,MSL 等级/回流焊峰值温度:Level-3-260C-168 HR,引脚镀层/焊球材料:SN,TI官网DS90C241QVS/NOPB的批量USD价格:5.635(1000+)
DS90C241QVSX/NOPB,工作温度:-40 to 105,封装:TQFP (PFB)-48,包装数量MPQ:1000个,MSL 等级/回流焊峰值温度:Level-3-260C-168 HR,引脚镀层/焊球材料:SN,TI官网DS90C241QVSX/NOPB的批量USD价格:4.818(1000+)
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