- 制造厂商:TI
- 产品类别:接口
- 技术类目:高速串行器/解串器 - FPD-Link 串行器/解串器
- 功能描述:+3.3V LVDS 接收器 24 位平板显示器 (FPD) 链路 - 65MHz
- 点击这里打开及下载DS90CF384的技术文档资料
- TI代理渠道,提供当日发货、严格的质量标准,满足您的目标价格
The DS90C383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF384 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. The transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge transmitter will inter-operate with a Falling edge receiver (DS90CF384) without any translation logic. The DS90CF384 is also offered in 64 ball, 0.8mm fine pitch ball grid array(FBGA) package which provides a 44 % reduction in PCB footprint (available Q3, 1999).
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
- 20 to 65 MHz shift clock support
- Programmable transmitter (DS90C383) strobe select (Rising or Falling edge strobe)
- Single 3.3V supply
- Chipset (Tx + Rx) power consumption < 250 mW (typ)
- Power-down mode (< 0.5 mW total)
- Single pixel per clock XGA (1024x768) ready
- Supports VGA, SVGA, XGA and higher addressability.
- Up to 227 Megabytes/sec bandwidth
- Up to 1.8 Gbps throughput
- Narrow bus reduces cable size and cost
- 290 mV swing LVDS devices for low EMI
- PLL requires no external components
- Low profile 56-lead TSSOP package.
- DS90CF384 also available in 64 ball, 0.8mm fine pitch ball grid array(FBGA) package
- Falling edge data strobe Receiver
- Compatible with TIA/EIA-644 LVDS standard
- ESD rating >7 kV
- Operating Temperature: –40°C to +85°C
- Function
- Deserializer
- Color depth (bpp)
- 24
- Input compatibility
- FPD-Link LVDS
- Pixel clock frequency (Max) (MHz)
- 65
- Output compatibility
- LVCMOS
- Features
- Low-EMI Point-to-Point Communication
- EMI reduction
- LVDS
- Operating temperature range (C)
- -40 to 85
DS90CF384的完整型号有:DS90CF384MTD/NOPB、DS90CF384MTDX/NOPB,以下是这些产品的关键参数及官网采购报价:
DS90CF384MTD/NOPB,工作温度:-40 to 85,封装:TSSOP (DGG)-56,包装数量MPQ:34个,MSL 等级/回流焊峰值温度:Level-2-260C-1 YEAR,引脚镀层/焊球材料:SN,TI官网DS90CF384MTD/NOPB的批量USD价格:2.64(1000+)
DS90CF384MTDX/NOPB,工作温度:-40 to 85,封装:TSSOP (DGG)-56,包装数量MPQ:1000个,MSL 等级/回流焊峰值温度:Level-2-260C-1 YEAR,引脚镀层/焊球材料:SN,TI官网DS90CF384MTDX/NOPB的批量USD价格:2.218(1000+)
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FPD-Link evaluation kit contains a Transmitter (Tx) board, a Receiver (Rx) board along with interfacing cables. This kit will demonstrate the chipsets interfacing from test equipment or a graphics controller using Low Voltage Differential Signaling (LVDS) to a receiver board.
The Transmitter board (...)
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