The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side.

The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

• 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput)
• Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down Pins
• Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data)
• Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
• Line and Local Loopback Modes
• Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
• No External Coding Required
• Internal PLL, No External PLL Components Required
• Single +3.3V Power Supply
• Low Power: 90mA (typ) Transmitter, 100mA (typ) at 66 MHz with PRBS-15 Pattern
• ±100 mV Receiver Input Threshold
• Loss of Lock Detection and Reporting Pin
• Industrial ?40 to +85°C Temperature Range
• >2.0kV HBM ESD
• Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

• Function
• SerDes
• Protocols
• Channel-Link I
• Number of transmitters
• 1
• Number of receivers
• 1
• Supply voltage (V)
• 3.3
• Signaling rate (Mbps)
• 2376
• Input signal
• LVTTL, BLVDS
• Output signal
• LVDS, BLVDS, LVTTL
• Rating
• Catalog
• Operating temperature range (C)
• -40 to 85

DS92LV18的完整型号有：DS92LV18TVV/NOPB、DS92LV18TVVX/NOPB，以下是这些产品的关键参数及官网采购报价：

DS92LV18TVV/NOPB，工作温度：-40 to 85，封装：LQFP (PN)-80，包装数量MPQ：119个，MSL 等级/回流焊峰值温度：Level-3-260C-168 HR，引脚镀层/焊球材料：SN，TI官网DS92LV18TVV/NOPB的批量USD价格：8.809（1000+）

DS92LV18TVVX/NOPB，工作温度：-40 to 85，封装：LQFP (PN)-80，包装数量MPQ：1000个，MSL 等级/回流焊峰值温度：Level-3-260C-168 HR，引脚镀层/焊球材料：SN，TI官网DS92LV18TVVX/NOPB的批量USD价格：7.454（1000+）

LVDS-18B-EVK — 18 位总线 LVDS SERDES 评估板 15-66 MHz

The LVDS-18B-EVK is a complete kit for evaluation of National Semiconductor's 18-bit SerDes devices (DS92LV18 and SCAN921821) with low cost twisted pair cables as well as other 100-ohm differential cables.

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice

PSpice for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助?PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。

在?PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)

TINA-TI — 基于 SPICE 的模拟仿真程序

TINA-TI 提供了 SPICE 所有的传统直流、瞬态和频域分析以及更多。TINA 具有广泛的后处理功能，允许您按照希望的方式设置结果的格式。虚拟仪器允许您选择输入波形、探针电路节点电压和波形。TINA 的原理图捕获非常直观 - 真正的“快速入门”。

TINA-TI 安装需要大约 500MB。直接安装，如果想卸载也很容易。我们相信您肯定会爱不释手。

TINA 是德州仪器 (TI) 专有的 DesignSoft 产品。该免费版本具有完整的功能，但不支持完整版 TINA 所提供的某些其他功能。

如需获取可用 TINA-TI 模型的完整列表，请参阅：SpiceRack - 完整列表

需要 HSpice (...)