SN54LVTH573_TI 具有三态输出的 3.3V ABT 八路透明 D 类锁存器

SN54LVTH573的基本参数

制造厂商：TI
产品类别：逻辑和电压转换
技术类目：触发器、锁存器和寄存器 - D 型锁存器
功能描述：具有三态输出的 3.3V ABT 八路透明 D 类锁存器
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SN54LVTH573的产品详情：

These octal latches are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

SN54LVTH573的优势和特性：

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation Down to 2.7 V
Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot Insertion
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

SN54LVTH573的参数（英文）：

Number of channels (#)
8
Technology Family
LVT
Supply voltage (Min) (V)
2.7
Supply voltage (Max) (V)
3.6
Input type
TTL-Compatible CMOS
Output type
3-State
Clock Frequency (Max) (MHz)
160
IOL (Max) (mA)
64
IOH (Max) (mA)
-32
ICC (Max) (uA)
5000
Features
Ultra high speed (tpd <5ns), Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Bus-hold, Flow-through pinout

SN54LVTH573具体的完整产品型号参数及价格（美元）：

SN54LVTH573的完整型号有：5962-9583101Q2A、5962-9583101QRA、5962-9583101QSA、SNJ54LVTH573FK、SNJ54LVTH573J、SNJ54LVTH573W，以下是这些产品的关键参数及官网采购报价：

5962-9583101Q2A，工作温度：-55 to 125，封装：LCCC (FK)-20，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网5962-9583101Q2A的批量USD价格：29.379（1000+）

5962-9583101QRA，工作温度：-55 to 125，封装：CDIP (J)-20，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网5962-9583101QRA的批量USD价格：25.617（1000+）

5962-9583101QSA，工作温度：-55 to 125，封装：CFP (W)-20，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网5962-9583101QSA的批量USD价格：33.718（1000+）

SNJ54LVTH573FK，工作温度：-55 to 125，封装：LCCC (FK)-20，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网SNJ54LVTH573FK的批量USD价格：29.379（1000+）

SNJ54LVTH573J，工作温度：-55 to 125，封装：CDIP (J)-20，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网SNJ54LVTH573J的批量USD价格：25.617（1000+）

SNJ54LVTH573W，工作温度：-55 to 125，封装：CFP (W)-20，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网SNJ54LVTH573W的批量USD价格：33.718（1000+）

SN54LVTH573的评估套件：

SN54LVTH573的电路图解：

SN54LVTH573的评估套件：