- 制造厂商：TI
- 产品类别：逻辑和电压转换
- 技术类目：触发器、锁存器和寄存器 - D 型锁存器
- 功能描述：具有三态输出的八路 D 类透明锁存器
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These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.
The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.
- Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package
- 3-State Bus-Driving Outputs
- Full Parallel Access for Loading
- Buffered Control Inputs
- Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374)
- P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and ’S374)
- Number of channels (#)
- 8
- Technology Family
- S
- Supply voltage (Min) (V)
- 4.75
- Supply voltage (Max) (V)
- 5.25
- Input type
- Bipolar
- Output type
- 3-State
- Clock Frequency (Max) (MHz)
- 75
- IOL (Max) (mA)
- 20
- IOH (Max) (mA)
- -6.5
- ICC (Max) (uA)
- 40000
- Features
- Very high speed (tpd 5-10ns)
SN54S373的完整型号有：SN54S373J、SNJ54S373FK、SNJ54S373J，以下是这些产品的关键参数及官网采购报价：
SN54S373J，工作温度：-55 to 125，封装：CDIP (J)-20，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网SN54S373J的批量USD价格：15.484（1000+）
SNJ54S373FK，工作温度：-55 to 125，封装：LCCC (FK)-20，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网SNJ54S373FK的批量USD价格：21.746（1000+）
SNJ54S373J，工作温度：-55 to 125，封装：CDIP (J)-20，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网SNJ54S373J的批量USD价格：19.914（1000+）
SN54S373J，工作温度：-55 to 125，封装：CDIP (J)-20，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网SN54S373J的批量USD价格：15.484（1000+）
SNJ54S373FK，工作温度：-55 to 125，封装：LCCC (FK)-20，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网SNJ54S373FK的批量USD价格：21.746（1000+）
SNJ54S373J，工作温度：-55 to 125，封装：CDIP (J)-20，包装数量MPQ：1个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：SNPB，TI官网SNJ54S373J的批量USD价格：19.914（1000+）
