The SN65LVDS311 serializer transmits 27 parallel input data over 1, 2, or 3 serial output links. The device pinout is optimized to interface with the OMAP3630 application processor. The device loads a shift register with the 24 pixel bits and 3 control bits from the parallel CMOS input interface. The data are latched into the device by the pixel clock, PCLK. In addition to the 27 bits, the device adds a parity bit and two reserved bits for a total number of 30 serial bits. The parity bit allows a receiver to detect single-bit errors. Odd parity is implemented.

The serial shift register is uploaded through 1, 2, or 3 serial outputs at 30, 15, or 10 times the pixel clock data rate. A copy of the pixel clock is output on an additional differential output. The serial data and clock are transmitted via Sub Low-Voltage Differential Signaling (SubLVDS) lines. The SN65LVDS311 supports three power modes (Shutdown, Standby and Active) to conserve power.

When transmitting, the PLL locks to the incoming pixel clock PCLK and generates an internal high-speed clock at the line rate of the data lines. The parallel data is latched on the rising edge of PCLK. The serialized data is presented on the serial outputs D0, D1, D2 with a recreation of the Pixel clock PCLK generated from the internal high-speed clock and output on the CLK output. If the input clock PCLK stops, the device enters a standby mode to conserve power.

Two Link-Select lines LS0 and LS1 control whether 1, 2 or 3 serial links are used. The TXEN input may be used to put the SN65LVDS311 in a shutdown mode. The SN65LVDS311 enters an active Standby mode if the input clock PCLK stops. This minimizes power consumption without the need for controlling an external pin. The SN65LVDS311 is characterized for operation over ambient air temperatures of -40°C to 85°C. All CMOS inputs offer failsafe to protect the input from damage during power-up and to avoid current flow into the device inputs during power-up.

• 2.8 × 2.8mm package size
• 1.8V input signal swing
• 24-Bit RGB Data, 3 Control Bits, 1 Parity Bit and 2 Reserved Bits Transmitted over 1, 2 or 3 Differential Lines
• SubLVDS Differential Voltage Levels
• Three Operating Modes to Conserve Power
  • Active-Mode QVGA 17.4mW (typ)
  • Active-Mode VGA 28.8mW (typ)
  • Shutdown Mode ≈ 0.5μA (typ)
  • Standby Mode ≈ 0.5μA (typ)
• ESD Rating > 3kV (HBM)
• Pixel Clock Range of 4MHz–65MHz
• Failsafe on all CMOS Inputs
• Typical Application: Cameras, Embedded Computers

• Function
• Serializer
• Protocols
• Channel-Link I
• Supply voltage (V)
• 1.8
• Signaling rate (Mbps)
• 1755
• Input signal
• CMOS
• Output signal
• LVDS
• Rating
• Catalog
• Operating temperature range (C)
• -40 to 85

SN65LVDS311的完整型号有：SN65LVDS311YFFR、SN65LVDS311YFFT，以下是这些产品的关键参数及官网采购报价：

SN65LVDS311YFFR，工作温度：-40 to 85，封装：DSBGA (YFF)-49，包装数量MPQ：3000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：SNAGCU，TI官网SN65LVDS311YFFR的批量USD价格：1.848（1000+）

SN65LVDS311YFFT，工作温度：-40 to 85，封装：DSBGA (YFF)-49，包装数量MPQ：250个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：SNAGCU，TI官网SN65LVDS311YFFT的批量USD价格：2.218（1000+）

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice

PSpice for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助?PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。

在?PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)

TINA-TI — 基于 SPICE 的模拟仿真程序

TINA-TI 提供了 SPICE 所有的传统直流、瞬态和频域分析以及更多。TINA 具有广泛的后处理功能，允许您按照希望的方式设置结果的格式。虚拟仪器允许您选择输入波形、探针电路节点电压和波形。TINA 的原理图捕获非常直观 - 真正的“快速入门”。

TINA-TI 安装需要大约 500MB。直接安装，如果想卸载也很容易。我们相信您肯定会爱不释手。

TINA 是德州仪器 (TI) 专有的 DesignSoft 产品。该免费版本具有完整的功能，但不支持完整版 TINA 所提供的某些其他功能。

如需获取可用 TINA-TI 模型的完整列表，请参阅：SpiceRack - 完整列表

需要 HSpice (...)