This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range.

The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits.

The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note.

The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from –40°C to 85°C.

• 400-Mbps Signaling Rate1 and 200-Mxfr/s Data Transfer Rate
• Operates With a Single 3.3-V Supply
• –4-V to 5-V Common-Mode Input Voltage Range
• Differential Input Thresholds <±50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range
• Integrated 110- Line Termination Resistors On LVDT Products
• TSSOP Packaging (33 Only)
• Complies With TIA/EIA-644 (LVDS)
• Active Failsafe Assures a High-Level Output With No Input
• Bus-Pin ESD Protection Exceeds 15 kV HBM
• Input Remains High-Impedance on Power Down
• TTL Inputs Are 5-V Tolerant
• Pin-Compatible With the AM26LS32, SN65LVDS32B, μA9637, SN65LVDS9637B

1 The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

• Function
• Receiver
• Protocols
• LVDS
• Number of transmitters
• 0
• Number of receivers
• 4
• Supply voltage (V)
• 3.3
• Signaling rate (Mbps)
• 400
• Input signal
• ECL, LVPECL, PECL
• Output signal
• LVTTL
• Rating
• Catalog
• Operating temperature range (C)
• -40 to 85

SN65LVDS33的完整型号有：SN65LVDS33D、SN65LVDS33DR、SN65LVDS33PW、SN65LVDS33PWR，以下是这些产品的关键参数及官网采购报价：

SN65LVDS33D，工作温度：-40 to 85，封装：SOIC (D)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN65LVDS33D的批量USD价格：1.151（1000+）

SN65LVDS33DR，工作温度：-40 to 85，封装：SOIC (D)-16，包装数量MPQ：2500个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN65LVDS33DR的批量USD价格：.959（1000+）

SN65LVDS33PW，工作温度：-40 to 85，封装：TSSOP (PW)-16，包装数量MPQ：90个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN65LVDS33PW的批量USD价格：1.151（1000+）

SN65LVDS33PWR，工作温度：-40 to 85，封装：TSSOP (PW)-16，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN65LVDS33PWR的批量USD价格：.959（1000+）

SN65LVDS31-33EVM — 用于 SN65LVDS31 和 SN65LVDS33 的评估模块

TI offers a series of low-voltage differential signaling (LVDS) evaluation modules (EVMs) designed for analysis of the electrical characteristics of LVDS drivers and receivers. Four unique EVMs are available to evaluate the different classes of LVDS devices offered by TI.

As seen in the Combination (...)

SN65LVDS33 IBIS Model (Rev. A)

PSpice for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

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在?PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)

TINA-TI — 基于 SPICE 的模拟仿真程序

TINA-TI 提供了 SPICE 所有的传统直流、瞬态和频域分析以及更多。TINA 具有广泛的后处理功能，允许您按照希望的方式设置结果的格式。虚拟仪器允许您选择输入波形、探针电路节点电压和波形。TINA 的原理图捕获非常直观 - 真正的“快速入门”。

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TINA 是德州仪器 (TI) 专有的 DesignSoft 产品。该免费版本具有完整的功能，但不支持完整版 TINA 所提供的某些其他功能。

如需获取可用 TINA-TI 模型的完整列表，请参阅：SpiceRack - 完整列表

需要 HSpice (...)

TIDA-060017 — 通过 LVDS 接口传输 SPI 信号参考设计

该参考设计展示了如何解决和优化信号完整性难题，通常在嘈杂环境中在同一个 PCB 上沿较长的距离发送 SPI 信号或从一个 PCB 向另一个电路板发送 SPI 信号（通过 LVDS 接口传输 SPI 信号）时会遇到这些难题。该概念具有高噪声抗扰性、更低的 EMI 发射和更宽的共模输入容差。