This family of 4-, 8-, or 16-differential line receivers (with optional integrated termination) implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail.

Any of the differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals almost always requires the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT products eliminate this external resistor by integrating it with the receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of receivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, the 8- or 16-channel driver (the SN65LVDS389 or SN65LVDS387, respectively), over 200 million data transfers per second in single-edge clocked systems are possible with little power.

The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

• Four- (’390), Eight- (’388A), or Sixteen- (’386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
• Integrated 110-Ω Line Termination Resistors on LVDT Products
• Designed for Signaling Rates Up to 250 Mbps
• SN65 Versions Bus-Terminal ESD Exceeds 15 kV
• Operates From a Single 3.3-V Supply
• Typical Propagation Delay Time of 2.6 ns
• Output Skew 100 ps (Typical) Part-To-Part Skew Is Less Than 1 ns
• LVTTL Levels Are 5-V Tolerant
• Open-Circuit Fail Safe
• Flow-Through Pinout
• Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch

• Function
• Receiver
• Protocols
• LVDS
• Number of transmitters
• 0
• Number of receivers
• 16
• Supply voltage (V)
• 3.3
• Signaling rate (Mbps)
• 250
• Input signal
• LVDS
• Output signal
• LVTTL
• Rating
• Catalog
• Operating temperature range (C)
• -40 to 85

SN65LVDT386的完整型号有：SN65LVDT386DGG、SN65LVDT386DGGR，以下是这些产品的关键参数及官网采购报价：

SN65LVDT386DGG，工作温度：-40 to 85，封装：TSSOP (DGG)-64，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：Level-2-260C-1 YEAR，引脚镀层/焊球材料：NIPDAU，TI官网SN65LVDT386DGG的批量USD价格：6.016（1000+）

SN65LVDT386DGGR，工作温度：-40 to 85，封装：TSSOP (DGG)-64，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-2-260C-1 YEAR，引脚镀层/焊球材料：NIPDAU，TI官网SN65LVDT386DGGR的批量USD价格：5.239（1000+）

SN65LVDS386EVM — 16 通道 LVDS 接收器评估模块

We have designed easy-to-use evaluation modules (EVM) forour 16-channel low-voltage differential signaling (LVDS) driver and receivers. Flexibility has been designed into these EVMs so they can be set up in a point-to-point topology (1 driver to 1 receiver) or a multidrop topology (1 driver (...)

SN65LVDT386, SN75LVDT386 IBIS Model (Rev. A)

PSpice for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助?PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。

在?PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)

TINA-TI — 基于 SPICE 的模拟仿真程序

TINA-TI 提供了 SPICE 所有的传统直流、瞬态和频域分析以及更多。TINA 具有广泛的后处理功能，允许您按照希望的方式设置结果的格式。虚拟仪器允许您选择输入波形、探针电路节点电压和波形。TINA 的原理图捕获非常直观 - 真正的“快速入门”。

TINA-TI 安装需要大约 500MB。直接安装，如果想卸载也很容易。我们相信您肯定会爱不释手。

TINA 是德州仪器 (TI) 专有的 DesignSoft 产品。该免费版本具有完整的功能，但不支持完整版 TINA 所提供的某些其他功能。

如需获取可用 TINA-TI 模型的完整列表，请参阅：SpiceRack - 完整列表

需要 HSpice (...)