The SN74AHC8541 8-bit inverting/non-inverting buffers are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.

All outputs are in the high-impedance state (disabled) when the output-enable (OE) input is high. When OE is low, the respective gate passes the data from the D input to its Y output.

The T/C input selects inverting or non-inverting data transfer. When the T/C input is high, it provides non-inverting buffers. When the T/C input is low, it provides inverting buffers when they are not in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

• Operating Range of 2 V to 5.5 V VCC
• 8-Bit Inverting/Non-Inverting Outputs
• 20-Pin Thin Shrink Small-Outline Package [TSSOP (PW)] and 20-Pin Plastic Dual-In-Line Package [PDIP (N)]

• Technology Family
• AHC
• Supply voltage (Min)
• 2
• Supply voltage (Max) (V)
• 5.5
• Number of channels (#)
• 8
• Inputs per channel
• 1
• IOL (Max) (mA)
• 12
• IOH (Max) (mA)
• -12
• Input type
• Standard CMOS
• Output type
• 3-State
• Features
• Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)
• Data rate (Max) (Mbps)
• 110
• Rating
• Catalog
• Operating temperature range (C)
• -40 to 85

SN74AHC8541的完整型号有：SN74AHC8541N，以下是这些产品的关键参数及官网采购报价：

SN74AHC8541N，工作温度：-40 to 85，封装：PDIP (N)-20，包装数量MPQ：20个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网SN74AHC8541N的批量USD价格：.457（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。