- 制造厂商：TI
- 产品类别：逻辑和电压转换
- 技术类目：触发器、锁存器和寄存器 - JK 触发器
- 功能描述：具有清零和预置端的双路负边沿触发式 J-K 触发器
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These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (
) or clear (
) inputs sets or resets the outputs, regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
The SN54ALS112A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS112A is characterized for operation from 0°C to 70°C.
- Fully Buffered to Offer Maximum Isolation From External Disturbance
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
- Number of channels (#)
- 2
- Technology Family
- ALS
- Supply voltage (Min) (V)
- 4.5
- Supply voltage (Max) (V)
- 5.5
- Input type
- TTL
- Output type
- Push-Pull
- Clock Frequency (MHz)
- 34
- ICC (Max) (uA)
- 4000
- IOL (Max) (mA)
- 8
- IOH (Max) (mA)
- -0.4
- Features
- Negative edge triggered, High speed (tpd 10-50ns), Preset, Clear
SN74ALS112A的完整型号有：SN74ALS112AD、SN74ALS112AN、SN74ALS112ANSR，以下是这些产品的关键参数及官网采购报价：
SN74ALS112AD，工作温度：0 to 70，封装：SOIC (D)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALS112AD的批量USD价格：0.483（1000+）
SN74ALS112AN，工作温度：0 to 70，封装：PDIP (N)-16，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALS112AN的批量USD价格：0.555（1000+）
SN74ALS112ANSR，工作温度：0 to 70，封装：SO (NS)-16，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALS112ANSR的批量USD价格：0.483（1000+）
14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM
该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
