The SN74ALS166 parallel-load 8-bit shift register is compatible with most other TTL logic families. All inputs are buffered to lower the drive requirements. Input clamping diodes minimize switching transients and simplify system design.

These parallel-in or serial-in, serial-out registers have a complexity of 77 equivalent gates on the chip. They feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR\) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD\) input. When high, SH/LD\ enables the serial data (SER) input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data (A-H) inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through a two-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running and the register can be stopped on command with the clock input. CLK INH should be changed to the high level only when CLK is high. The buffered CLR\ overrides all other inputs, including CLK, and sets all flip-flops to zero.

The SN74ALS166 is characterized for operation from 0°C to 70°C.

• Synchronous Load
• Direct Overriding Clear
• Parallel-to-Serial Conversion
• Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages and Standard Plastic (N) DIP

• Configuration
• Parallel-in, Serial-out
• Bits (#)
• 8
• Technology Family
• ALS
• Supply voltage (Min) (V)
• 4.5
• Supply voltage (Max) (V)
• 5.5
• Input type
• Bipolar
• Output type
• Push-Pull
• Clock Frequency (MHz)
• 45
• IOL (Max) (mA)
• 8
• IOH (Max) (mA)
• -0.4
• ICC (Max) (uA)
• 24000
• Features
• High speed (tpd 10-50ns)

SN74ALS166的完整型号有：SN74ALS166D、SN74ALS166DBR、SN74ALS166DR、SN74ALS166N、SN74ALS166NSR，以下是这些产品的关键参数及官网采购报价：

SN74ALS166D，工作温度：0 to 70，封装：SOIC (D)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALS166D的批量USD价格：2.478（1000+）

SN74ALS166DBR，工作温度：0 to 70，封装：SSOP (DB)-16，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALS166DBR的批量USD价格：2.272（1000+）

SN74ALS166DR，工作温度：0 to 70，封装：SOIC (D)-16，包装数量MPQ：2500个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALS166DR的批量USD价格：2.065（1000+）

SN74ALS166N，工作温度：0 to 70，封装：PDIP (N)-16，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALS166N的批量USD价格：2.375（1000+）

SN74ALS166NSR，工作温度：0 to 70，封装：SO (NS)-16，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALS166NSR的批量USD价格：2.375（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。