- 制造厂商:TI
- 产品类别:逻辑和电压转换
- 技术类目:缓冲器、驱动器和收发器 - 反向缓冲器和驱动器
- 功能描述:具有三态输出的 8 通道、4.5V 至 5.5V 双极反相器
- 点击这里打开及下载SN74ALS540的技术文档资料
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These octal buffers and line drivers are designed to have the performance of the popular SN54ALS240A/ SN74ALS240A series and, at the same time, offer a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout.
The 3-state control gate is a 2-input NOR gate such that, if either output-enable (OE1\ or OE2\) input is high, all eight outputs are in the high-impedance state.
The SN74ALS540 provides inverted data. The ALS541 provide true data at the outputs.
The 1 versions of SN74ALS540 and SN74ALS541 are identical to the standard versions, except that the recommended maximum IOL is increased to 48 mA. There is no 1 version of the SN54ALS541.
- 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
- pnp Inputs Reduce dc Loading
- Data Flowthrough Pinout (All Inputs on Opposite Side From Outputs)
- Technology Family
- ALS
- Supply voltage (Min) (V)
- 4.5
- Supply voltage (Max) (V)
- 5.5
- Number of channels (#)
- 8
- IOL (Max) (mA)
- 24
- IOH (Max) (mA)
- -15
- ICC (Max) (uA)
- 25000
- Input type
- Bipolar
- Output type
- 3-State
- Features
- Very high speed (tpd 5-10ns)
- Rating
- Catalog
SN74ALS540的完整型号有:SN74ALS540DW、SN74ALS540DWR、SN74ALS540N、SN74ALS540NSR,以下是这些产品的关键参数及官网采购报价:
SN74ALS540DW,工作温度:0 to 70,封装:SOIC (DW)-20,包装数量MPQ:25个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74ALS540DW的批量USD价格:1.268(1000+)
SN74ALS540DWR,工作温度:0 to 70,封装:SOIC (DW)-20,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74ALS540DWR的批量USD价格:1.057(1000+)
SN74ALS540N,工作温度:0 to 70,封装:PDIP (N)-20,包装数量MPQ:20个,MSL 等级/回流焊峰值温度:N/A for Pkg Type,引脚镀层/焊球材料:NIPDAU,TI官网SN74ALS540N的批量USD价格:1.216(1000+)
SN74ALS540NSR,工作温度:0 to 70,封装:SO (NS)-20,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74ALS540NSR的批量USD价格:1.216(1000+)
14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM
该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。