- 制造厂商:TI
- 产品类别:逻辑和电压转换
- 技术类目:触发器、锁存器和寄存器 - D 型触发器
- 功能描述:具有清零和预置端的双路正边沿触发式 D 型触发器
- 点击这里打开及下载SN74ALS74A的技术文档资料
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These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
- Number of channels (#)
- 2
- Technology Family
- ALS
- Supply voltage (Min) (V)
- 4.5
- Supply voltage (Max) (V)
- 5.5
- Input type
- Bipolar
- Output type
- Push-Pull
- Clock Frequency (Max) (MHz)
- 70
- IOL (Max) (mA)
- 8
- IOH (Max) (mA)
- -0.4
- ICC (Max) (uA)
- 4000
- Features
- High speed (tpd 10-50ns)
SN74ALS74A的完整型号有:SN74ALS74AD、SN74ALS74ADR、SN74ALS74AN、SN74ALS74ANSR,以下是这些产品的关键参数及官网采购报价:
SN74ALS74AD,工作温度:0 to 70,封装:SOIC (D)-14,包装数量MPQ:50个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74ALS74AD的批量USD价格:0.302(1000+)
SN74ALS74ADR,工作温度:0 to 70,封装:SOIC (D)-14,包装数量MPQ:2500个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74ALS74ADR的批量USD价格:0.252(1000+)
SN74ALS74AN,工作温度:0 to 70,封装:PDIP (N)-14,包装数量MPQ:25个,MSL 等级/回流焊峰值温度:N/A for Pkg Type,引脚镀层/焊球材料:NIPDAU,TI官网SN74ALS74AN的批量USD价格:0.29(1000+)
SN74ALS74ANSR,工作温度:0 to 70,封装:SO (NS)-14,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74ALS74ANSR的批量USD价格:0.29(1000+)
14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM
该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。