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SN74ALS873B的基本参数
  • 制造厂商:TI
  • 产品类别:逻辑和电压转换
  • 技术类目:触发器、锁存器和寄存器 - D 型锁存器
  • 功能描述:具有三态输出的双路 4 位 D 类锁存器
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SN74ALS873B的产品详情:

These dual 4-bit D-type latches feature 3-state outputs designed specifically for bus driving. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The dual 4-bit latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs in true form, according to the function table. When LE is low, the outputs are latched. When the clear () input goes low, the Q outputs go low independently of LE. The outputs are in the high-impedance state when the output-enable () input is at a high logic level.

The SN54ALS873B and SN54AS873A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS873B and SN74AS873A are characterized for operation from 0°C to 70°C.

 

 

SN74ALS873B的优势和特性:
  • 3-State Buffer-Type Outputs Drive Bus Lines Directly
  • Bus-Structured Pinout
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

SN74ALS873B的参数(英文):
  • Number of channels (#)
  • 8
  • Technology Family
  • ALS
  • Supply voltage (Min) (V)
  • 4.5
  • Supply voltage (Max) (V)
  • 5.5
  • Input type
  • Bipolar
  • Output type
  • 3-State
  • Clock Frequency (Max) (MHz)
  • 75
  • IOL (Max) (mA)
  • 24
  • IOH (Max) (mA)
  • -2.6
  • ICC (Max) (uA)
  • 32000
  • Features
  • High speed (tpd 10-50ns), Flow-through pinout
SN74ALS873B具体的完整产品型号参数及价格(美元):

SN74ALS873B的完整型号有:SN74ALS873BDW、SN74ALS873BDWR,以下是这些产品的关键参数及官网采购报价:

SN74ALS873BDW,工作温度:0 to 70,封装:SOIC (DW)-24,包装数量MPQ:25个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74ALS873BDW的批量USD价格:2.869(1000+)

SN74ALS873BDWR,工作温度:0 to 70,封装:SOIC (DW)-24,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74ALS873BDWR的批量USD价格:2.391(1000+)

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SN74ALS873B的评估套件:

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

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