This 9-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. In addition, this device provides a 3-state buffer-type output and is easily implemented in parity applications.

The nine latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. The Q outputs are in the 3-state condition when the output-enable () input is high.

Read back is provided through the output-enable () input. When is taken low, the data present at the output of the data latches is allowed to pass back onto the input data bus. When is taken high, the output of the data latches is isolated from the D inputs. does not affect the internal operation of the latches; however, precautions should be taken not to create a bus conflict.

The SN74ALS992 is characterized for operation from 0°C to 70°C.

• 3-State I/O-Type Read-Back Inputs
• Bus-Structured Pinout
• True Logic Outputs
• Designed With Nine Bits for Parity Applications
• Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs

• Number of channels (#)
• 9
• Technology Family
• ALS
• Supply voltage (Min) (V)
• 4.5
• Supply voltage (Max) (V)
• 5.5
• Input type
• Bipolar
• Output type
• 3-State
• Clock Frequency (Max) (MHz)
• 75
• IOL (Max) (mA)
• 24
• IOH (Max) (mA)
• -2.6
• ICC (Max) (uA)
• 80000
• Features
• High speed (tpd 10-50ns), Flow-through pinout

SN74ALS992的完整型号有：SN74ALS992DW，以下是这些产品的关键参数及官网采购报价：

SN74ALS992DW，工作温度：0 to 70，封装：SOIC (DW)-24，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALS992DW的批量USD价格：7.501（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。