- 制造厂商：TI
- 产品类别：逻辑和电压转换
- 技术类目：缓冲器、驱动器和收发器 - 通用收发器
- 功能描述：具有三态输出的 18 位通用总线收发器
- 点击这里打开及下载SN74ALVCH162601的技术文档资料
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This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH162601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, CLKBA, and CLKENBA\.
The B-port outputs include equivalent 26-
series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162601 is characterized for operation from –0°C to 85°C.
- Member of the Texas Instruments Widebus? Family
- EPIC? (Enhanced-Performance Implanted CMOS) Submicron Process
- UBT? (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes
- B-Port Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
NOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR. Widebus, EPIC, UBT are trademarks of Texas Instruments.
- IOL (Max) (mA)
- 12
- IOH (Max) (mA)
- -32
- Technology Family
- ALVC
- Rating
- Catalog
- Operating temperature range (C)
- -40 to 85
SN74ALVCH162601的完整型号有：SN74ALVCH162601DL、SN74ALVCH162601DLR、SN74ALVCH162601GR，以下是这些产品的关键参数及官网采购报价：
SN74ALVCH162601DL，工作温度：-40 to 85，封装：SSOP (DL)-56，包装数量MPQ：20个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALVCH162601DL的批量USD价格：.497（1000+）
SN74ALVCH162601DLR，工作温度：-40 to 85，封装：SSOP (DL)-56，包装数量MPQ：1000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALVCH162601DLR的批量USD价格：.414（1000+）
SN74ALVCH162601GR，工作温度：-40 to 85，封装：TSSOP (DGG)-56，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALVCH162601GR的批量USD价格：.414（1000+）
SN74ALVCH162601DL，工作温度：-40 to 85，封装：SSOP (DL)-56，包装数量MPQ：20个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALVCH162601DL的批量USD价格：.497（1000+）
SN74ALVCH162601DLR，工作温度：-40 to 85，封装：SSOP (DL)-56，包装数量MPQ：1000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALVCH162601DLR的批量USD价格：.414（1000+）
SN74ALVCH162601GR，工作温度：-40 to 85，封装：TSSOP (DGG)-56，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALVCH162601GR的批量USD价格：.414（1000+）
