- 制造厂商：TI
- 产品类别：逻辑和电压转换
- 技术类目：触发器、锁存器和寄存器 - D 型触发器
- 功能描述：具有三态输出的 16 位边沿 D 类触发器
- 点击这里打开及下载SN74ALVCH16374的技术文档资料
- TI代理渠道，提供当日发货、严格的质量标准，满足您的目标价格
This 16-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. OE\ can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
- Member of the Texas Instruments Widebus? Family
- Operates From 1.65 to 3.6 V
- Max tpd of 4.2 ns at 3.3 V
- ±24-mA Output Drive at 3.3 V
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
Widebus is a trademark of Texas Instruments.
- Number of channels (#)
- 16
- Technology Family
- ALVC
- Supply voltage (Min) (V)
- 1.65
- Supply voltage (Max) (V)
- 3.6
- Input type
- Standard CMOS
- Output type
- 3-State
- Clock Frequency (Max) (MHz)
- 150
- IOL (Max) (mA)
- 24
- IOH (Max) (mA)
- -24
- ICC (Max) (uA)
- 40
- Features
- Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Bus-hold
SN74ALVCH16374的完整型号有：SN74ALVCH16374DGGR、SN74ALVCH16374DGVR、SN74ALVCH16374DL、SN74ALVCH16374DLR，以下是这些产品的关键参数及官网采购报价：
SN74ALVCH16374DGGR，工作温度：-40 to 85，封装：TSSOP (DGG)-48，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALVCH16374DGGR的批量USD价格：.543（1000+）
SN74ALVCH16374DGVR，工作温度：-40 to 85，封装：TVSOP (DGV)-48，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALVCH16374DGVR的批量USD价格：.543（1000+）
SN74ALVCH16374DL，工作温度：-40 to 85，封装：SSOP (DL)-48，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALVCH16374DL的批量USD价格：.706（1000+）
SN74ALVCH16374DLR，工作温度：-40 to 85，封装：SSOP (DL)-48，包装数量MPQ：1000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALVCH16374DLR的批量USD价格：.597（1000+）
HSPICE Model for SN74ALVCH16374
Acontis EC-Master EtherCAT Master 堆栈是一种可移植度非常高的软件堆栈，可在各种嵌入式平台上使用。EC-Master 支持高性能的 TI Sitara MPU，可提供先进的 EtherCAT Master 解决方案，客户可使用该解决方案来实施 EtherCAT 通信接口电路板、基于 EtherCAT 的 PLC 或运动控制应用。EC-Master 结构设计让用户无需计划额外的任务，因此即使在没有操作系统的平台（例如 AM335x 上支持的 TI Starterware）上也可以使用全部堆栈功能。这种架构结合高速以太网驱动器让用户能在 Sitara 平台上实施 (...)TIDEP0054 — 适用于变电站自动化的并行冗余协议 (PRP) 以太网参考设计
此参考设计为智能电网输电和配电网络中的变电站自动化设备提供高可靠性、低延迟网络通信。它支持 IEC 62439 标准中使用 PRU-ICSS 的并行冗余协议 (PRP) 规范。此参考设计是 FPGA 方法的较低成本替代方法，可提供在无需额外组件的情况下添加 IEC 61850 支持等功能的灵活性和性能。
