This device contains four independent noninverting buffers and an 8-bit noninverting bus transceiver and D-type latch, designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH16973 is particularly suitable for demultiplexing an address/data bus into a dedicated address bus and dedicated data bus. The device is used where there is asynchronous bidirectional communication between the A and B data bus, and the address signals are latched and buffered on the Q bus. The control-function implementation minimizes external timing requirements.

This device can be used as one 4-bit buffer, one 8-bit transceiver, and one 8-bit latch. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The transceiver output-enable (TOE)\ input can be used to disable the transceivers so that the A and B buses effectively are isolated.

When the latch-enable (LE) input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE)\ input can be used to place the nine Q outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, LOE\ and TOE\ should be tied to V_CC through pullup resistors; the minimum values of the resistors are determined by the current-sinking capability of the drivers.

The four independent noninverting buffers perform the Boolean function Y = D and are independent of the state of DIR, TOE\, LE, and LOE\.

The A and B I/Os, and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

• Member of the Texas Instruments Widebus? Family
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

• IOL (Max) (mA)
• 24
• IOH (Max) (mA)
• -24
• Technology Family
• ALVC
• Rating
• Catalog
• Operating temperature range (C)
• -40 to 85

SN74ALVCH16973的完整型号有：SN74ALVCH16973DGGR，以下是这些产品的关键参数及官网采购报价：

SN74ALVCH16973DGGR，工作温度：-40 to 85，封装：TSSOP (DGG)-48，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALVCH16973DGGR的批量USD价格：1.088（1000+）

SN74ALVCH16973DGGR，工作温度：-40 to 85，封装：TSSOP (DGG)-48，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALVCH16973DGGR的批量USD价格：1.088（1000+）