This octal buffer/driver is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUCH244 is organized as two 4-bit line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• Ioff Supports Partial-Power-Down Mode Operation
• Sub 1-V Operable
• Max tpd of 1.9 ns at 1.8 V
• Low Power Consumption, 20-μA Max ICC
• ±8-mA Output Drive at 1.8 V
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

• Technology Family
• AUC
• Supply voltage (Min) (V)
• 0.8
• Supply voltage (Max) (V)
• 2.7
• Number of channels (#)
• 8
• IOL (Max) (mA)
• 9
• ICC (Max) (uA)
• 20
• IOH (Max) (mA)
• -9
• Input type
• Standard CMOS
• Output type
• 3-State
• Features
• Balanced outputs, Ultra high speed (tpd <5ns), Partial power down (Ioff), Over-voltage tolerant inputs, Bus-hold
• Rating
• Catalog

SN74AUCH244的完整型号有：SN74AUCH244RGYR，以下是这些产品的关键参数及官网采购报价：

SN74AUCH244RGYR，工作温度：-40 to 85，封装：VQFN (RGY)-20，包装数量MPQ：3000个，MSL 等级/回流焊峰值温度：Level-2-260C-1 YEAR，引脚镀层/焊球材料：NIPDAU，TI官网SN74AUCH244RGYR的批量USD价格：.48（1000+）

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.

SN74AUCH244 IBIS Model

此参考设计展示了如何以低 BOM 成本实现高采样率和高分辨率的多个交错式 ADC。构建此参考设计时考虑到了电子成像系统。高清成像和其他高速信号处理应用需要使用 ADC，方可实现高分辨率、高信噪比、高速和低功耗等特性。借助单个芯片无法始终满足这些要求。通过交错多个 SAR ADC，该设计可优化不同 ADC 间的折衷，以满足所有系统要求。