These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control function implementation allows for maximum flexibility in timing.

These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the enable inputs (G\BA and GAB).

The enable inputs can be used to disable the device so that the buses are effectively isolated.

The dual-enable configuration gives the 'LS620, 'LS621, and 'LS623 the capability to store data by simultaneous enabling of G\BA and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses will be identical for the 'LS621 and 'LS623 devices or complementary for the 'LS620.

• Bidirectional Bus Transceivers in High-Density 20-Pin Packages
• Local Bus-Latch Capability
• Hysteresis at Bus Inputs Improves Noise Margins
• Choice of True or Inverting Logic
• Choice of 3-State or Open-Collector Outputs

• IOL (Max) (mA)
• 24
• IOH (Max) (mA)
• -15
• Technology Family
• LS
• Rating
• Catalog
• Operating temperature range (C)
• 0 to 70

SN74LS623的完整型号有：SN74LS623N，以下是这些产品的关键参数及官网采购报价：

SN74LS623N，工作温度：0 to 70，封装：PDIP (N)-20，包装数量MPQ：20个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网SN74LS623N的批量USD价格：2.692（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。