This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V V_CC operation.

The SN74LV08A performs the Boolean function Y = A • B or Y = (A\ + B\) in positive logic.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Qualified for Automotive Applications
• Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
• Supports Mixed-Mode Voltage Operation on All Ports
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

• Technology Family
• LV-A
• Supply voltage (Min) (V)
• 2
• Supply voltage (Max) (V)
• 5.5
• Number of channels (#)
• 4
• Inputs per channel
• 2
• IOL (Max) (mA)
• 12
• IOH (Max) (mA)
• -12
• Input type
• Standard CMOS
• Output type
• Push-Pull
• Features
• Partial power down (Ioff), Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)
• Data rate (Max) (Mbps)
• 70
• Rating
• Automotive
• Operating temperature range (C)
• -40 to 105

SN74LV08A-Q1的完整型号有：SN74LV08ATPWRG4Q1，以下是这些产品的关键参数及官网采购报价：

SN74LV08ATPWRG4Q1，工作温度：-40 to 105，封装：TSSOP (PW)-14，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV08ATPWRG4Q1的批量USD价格：.202（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。