- 制造厂商:TI
- 产品类别:逻辑和电压转换
- 技术类目:触发器、锁存器和寄存器 - 移位寄存器
- 功能描述:8 位并行负载移位寄存器
- 点击这里打开及下载SN74LV166A的技术文档资料
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The 'LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V VCC operation.
The 'LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR\) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD\) input. When high, SH/LD\ enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR\ overrides all other inputs, including CLK, and resets all flip-flops to zero.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
- 2-V to 5.5-V VCC Operation
- Max tpd of 10.5 ns at 5 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C
- Ioff Supports Partial-Power-Down-Mode Operation
- Synchronous Load
- Direct Overriding Clear
- Parallel-to-Serial Conversion
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Configuration
- Parallel-in, Serial-out
- Bits (#)
- 8
- Technology Family
- LV-A
- Supply voltage (Min) (V)
- 2
- Supply voltage (Max) (V)
- 5.5
- Input type
- Standard CMOS
- Output type
- Push-Pull
- Clock Frequency (MHz)
- 45
- IOL (Max) (mA)
- 12
- IOH (Max) (mA)
- -12
- ICC (Max) (uA)
- 20
- Features
- Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff)
SN74LV166A的完整型号有:SN74LV166AD、SN74LV166ADBR、SN74LV166ADGVR、SN74LV166ADR、SN74LV166ANSR、SN74LV166APW、SN74LV166APWR,以下是这些产品的关键参数及官网采购报价:
SN74LV166AD,工作温度:-40 to 85,封装:SOIC (D)-16,包装数量MPQ:40个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74LV166AD的批量USD价格:.43(1000+)
SN74LV166ADBR,工作温度:-40 to 85,封装:SSOP (DB)-16,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74LV166ADBR的批量USD价格:.394(1000+)
SN74LV166ADGVR,工作温度:-40 to 85,封装:TVSOP (DGV)-16,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74LV166ADGVR的批量USD价格:.358(1000+)
SN74LV166ADR,工作温度:-40 to 85,封装:SOIC (D)-16,包装数量MPQ:2500个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74LV166ADR的批量USD价格:.358(1000+)
SN74LV166ANSR,工作温度:-40 to 85,封装:SO (NS)-16,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74LV166ANSR的批量USD价格:.394(1000+)
SN74LV166APW,工作温度:-40 to 85,封装:TSSOP (PW)-16,包装数量MPQ:90个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74LV166APW的批量USD价格:.43(1000+)
SN74LV166APWR,工作温度:-40 to 85,封装:TSSOP (PW)-16,包装数量MPQ:2000个,MSL 等级/回流焊峰值温度:Level-1-260C-UNLIM,引脚镀层/焊球材料:NIPDAU,TI官网SN74LV166APWR的批量USD价格:.358(1000+)
14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM
该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。