The SN74LV373AT is an octal transparent D-type latch. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Inputs Are TTL-Voltage Compatible
• 4.5-V to 5.5-V VCC Operation
• Typical tpd of 5.1 ns at 5 V
• Typical VOLP (Output Ground Bounce)<0.8 V at VCC = 5 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)>2.3 V at VCC = 5 V, TA = 25°C
• Supports Mixed-Mode Voltage Operation on All Ports
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

• Number of channels (#)
• 8
• Technology Family
• LV-AT
• Supply voltage (Min) (V)
• 4.5
• Supply voltage (Max) (V)
• 5.5
• Input type
• TTL-Compatible CMOS
• Output type
• 3-State
• Clock Frequency (Max) (MHz)
• 70
• IOL (Max) (mA)
• 16
• IOH (Max) (mA)
• -16
• ICC (Max) (uA)
• 20
• Features
• Balanced outputs, High speed (tpd 10-50ns), Partial power down (Ioff)

SN74LV373AT的完整型号有：SN74LV373ATDWR、SN74LV373ATNSR、SN74LV373ATPWR，以下是这些产品的关键参数及官网采购报价：

SN74LV373ATDWR，工作温度：-40 to 125，封装：SOIC (DW)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV373ATDWR的批量USD价格：.187（1000+）

SN74LV373ATNSR，工作温度：-40 to 125，封装：SO (NS)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV373ATNSR的批量USD价格：.14（1000+）

SN74LV373ATPWR，工作温度：-40 to 125，封装：TSSOP (PW)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV373ATPWR的批量USD价格：.104（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.