The SN74LV541AT is designed for 4.5-V to 5.5-V V_CC operation. The inputs are TTL-voltage compatible, which allows them to be interfaced with bipolar outputs and 3.3-V devices. The device also can be used to translate from 3.3 V to 5 V.

This device is ideal for driving bus lines or buffer memory address registers. It features inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.

The 3-state control gate is a two-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide noninverted data when they are not in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Inputs Are TTL-Voltage Compatible
• 4.5-V to 5.5-V VCC Operation
• Typical tpd of 4 ns at 5 V
• Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 5 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 5 V, TA = 25°C
• Supports Mixed-Mode Voltage Operation on All Ports
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

• Technology Family
• LV-AT
• Supply voltage (Min) (V)
• 4.5
• Supply voltage (Max) (V)
• 5.5
• Number of channels (#)
• 8
• IOL (Max) (mA)
• 16
• ICC (Max) (uA)
• 20
• IOH (Max) (mA)
• -16
• Input type
• TTL-Compatible CMOS
• Output type
• 3-State
• Features
• Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs
• Rating
• Catalog

SN74LV541AT的完整型号有：SN74LV541ATDBR、SN74LV541ATDGVR、SN74LV541ATDW、SN74LV541ATDWR、SN74LV541ATNSR、SN74LV541ATPW、SN74LV541ATPWR、SN74LV541ATPWT、SN74LV541ATRGYR，以下是这些产品的关键参数及官网采购报价：

SN74LV541ATDBR，工作温度：-40 to 125，封装：SSOP (DB)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV541ATDBR的批量USD价格：.3（1000+）

SN74LV541ATDGVR，工作温度：-40 to 125，封装：TVSOP (DGV)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV541ATDGVR的批量USD价格：.273（1000+）

SN74LV541ATDW，工作温度：-40 to 125，封装：SOIC (DW)-20，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV541ATDW的批量USD价格：.328（1000+）

SN74LV541ATDWR，工作温度：-40 to 125，封装：SOIC (DW)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV541ATDWR的批量USD价格：.273（1000+）

SN74LV541ATNSR，工作温度：-40 to 125，封装：SO (NS)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV541ATNSR的批量USD价格：.3（1000+）

SN74LV541ATPW，工作温度：-40 to 125，封装：TSSOP (PW)-20，包装数量MPQ：70个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV541ATPW的批量USD价格：.328（1000+）

SN74LV541ATPWR，工作温度：-40 to 125，封装：TSSOP (PW)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV541ATPWR的批量USD价格：.273（1000+）

SN74LV541ATPWT，工作温度：-40 to 125，封装：TSSOP (PW)-20，包装数量MPQ：250个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV541ATPWT的批量USD价格：.328（1000+）

SN74LV541ATRGYR，工作温度：-40 to 85，封装：VQFN (RGY)-20，包装数量MPQ：3000个，MSL 等级/回流焊峰值温度：Level-2-260C-1 YEAR，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV541ATRGYR的批量USD价格：.287（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.