This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V V_CC operation.

The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.

A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

• Operates From 1.65 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max tpd of 7.3 ns at 3.3 V
• Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
• Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)

• Number of channels (#)
• 10
• Technology Family
• LVC
• Supply voltage (Min) (V)
• 1.65
• Supply voltage (Max) (V)
• 3.6
• Input type
• Standard CMOS
• Output type
• 3-State
• Clock Frequency (Max) (MHz)
• 150
• IOL (Max) (mA)
• 24
• IOH (Max) (mA)
• -24
• ICC (Max) (uA)
• 10
• Features
• Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff)

SN74LVC821A的完整型号有：SN74LVC821ADBR、SN74LVC821ADGVR、SN74LVC821ADW、SN74LVC821ADWR、SN74LVC821APW、SN74LVC821APWR、SN74LVC821APWT，以下是这些产品的关键参数及官网采购报价：

SN74LVC821ADBR，工作温度：-40 to 85，封装：SSOP (DB)-24，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVC821ADBR的批量USD价格：.503（1000+）

SN74LVC821ADGVR，工作温度：-40 to 85，封装：TVSOP (DGV)-24，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVC821ADGVR的批量USD价格：.457（1000+）

SN74LVC821ADW，工作温度：-40 to 85，封装：SOIC (DW)-24，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVC821ADW的批量USD价格：.549（1000+）

SN74LVC821ADWR，工作温度：-40 to 85，封装：SOIC (DW)-24，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVC821ADWR的批量USD价格：.457（1000+）

SN74LVC821APW，工作温度：-40 to 85，封装：TSSOP (PW)-24，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVC821APW的批量USD价格：.549（1000+）

SN74LVC821APWR，工作温度：-40 to 85，封装：TSSOP (PW)-24，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVC821APWR的批量USD价格：.457（1000+）

SN74LVC821APWT，工作温度：-40 to 85，封装：TSSOP (PW)-24，包装数量MPQ：250个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVC821APWT的批量USD价格：.549（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。