These octal transceivers are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The 'LVT543 contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (or) and output-enable(or) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable () input must be low in order to enter data from A or to output data from B. If is low and is low, the A-to-B latches are transparent; a subsequent low-to-high transition of puts the A latches in the storage mode. With and both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the ,, and inputs.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVT543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN54LVT543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT543 is characterized for operation from -40°C to 85°C.

• State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation
• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
• Support Unregulated Battery Operation Down to 2.7 V
• Typical VOLP (Output Ground Bounce)< 0.8 V at VCC = 3.3 V, TA = 25°C
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors
• Support Live Insertion
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic (JT) DIPs

• IOL (Max) (mA)
• 64
• IOH (Max) (mA)
• -32
• Technology Family
• LVT
• Rating
• Catalog
• Operating temperature range (C)
• -40 to 85

SN74LVT543的完整型号有：SN74LVT543DW，以下是这些产品的关键参数及官网采购报价：

SN74LVT543DW，工作温度：-40 to 85，封装：SOIC (DW)-24，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVT543DW的批量USD价格：0.869（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。