These octal latches are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

When V_CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
• Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
• Support Unregulated Battery Operation Down to 2.7 V
• Ioff and Power-Up 3-State Support Hot Insertion
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 500 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)

• Number of channels (#)
• 8
• Technology Family
• LVT
• Supply voltage (Min) (V)
• 2.7
• Supply voltage (Max) (V)
• 3.6
• Input type
• TTL-Compatible CMOS
• Output type
• 3-State
• Clock Frequency (Max) (MHz)
• 160
• IOL (Max) (mA)
• 64
• IOH (Max) (mA)
• -32
• ICC (Max) (uA)
• 5000
• Features
• Ultra high speed (tpd <5ns), Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Bus-hold

SN74LVTH373的完整型号有：SN74LVTH373DBR、SN74LVTH373DW、SN74LVTH373DWR、SN74LVTH373NSR、SN74LVTH373PW、SN74LVTH373PWR，以下是这些产品的关键参数及官网采购报价：

SN74LVTH373DBR，工作温度：-40 to 85，封装：SSOP (DB)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVTH373DBR的批量USD价格：.263（1000+）

SN74LVTH373DW，工作温度：-40 to 85，封装：SOIC (DW)-20，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVTH373DW的批量USD价格：.286（1000+）

SN74LVTH373DWR，工作温度：-40 to 85，封装：SOIC (DW)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVTH373DWR的批量USD价格：.239（1000+）

SN74LVTH373NSR，工作温度：-40 to 85，封装：SO (NS)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVTH373NSR的批量USD价格：.263（1000+）

SN74LVTH373PW，工作温度：-40 to 85，封装：TSSOP (PW)-20，包装数量MPQ：70个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVTH373PW的批量USD价格：.286（1000+）

SN74LVTH373PWR，工作温度：-40 to 85，封装：TSSOP (PW)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LVTH373PWR的批量USD价格：.239（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。