These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS112A and SN74S112A are characterized for operation from 0°C to 70°C.

• Fully Buffered to Offer Maximum Isolation from External Disturbance
• Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability

• Number of channels (#)
• 2
• Technology Family
• S
• Supply voltage (Min) (V)
• 4.75
• Supply voltage (Max) (V)
• 5.25
• Input type
• TTL
• Output type
• Push-Pull
• Clock Frequency (MHz)
• 125
• ICC (Max) (uA)
• 25000
• IOL (Max) (mA)
• 20
• IOH (Max) (mA)
• -1
• Features
• Negative edge triggered, High speed (tpd 10-50ns), Preset, Clear

SN74S112A的完整型号有：SN74S112AN，以下是这些产品的关键参数及官网采购报价：

SN74S112AN，工作温度：0 to 70，封装：PDIP (N)-16，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网SN74S112AN的批量USD价格：.726（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。